NXP Semiconductors PXN2020, Reference Manual, Page: 687 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-73
26.5.2.67.30 Protocol Configuration Register 29 (PCR29)
26.5.2.67.31 Protocol Configuration Register 30 (PCR30)
26.5.2.68 Message Buffer Configuration, Control, Status Registers (MBCCSRn)
The content of these registers comprises message buffer configuration data, message buffer control data,
message buffer status information, and message buffer interrupt flags. A detailed description of all flags
can be found in
Section 26.6.6, Individual Message Buffer Functional Description.
If the application writes 1 to the EDT bit, no write access to the other register bits is performed.
If the application writes 0 to the EDT bit and 1 to the LCKT bit, no write access to the other bits is
performed.
Base + 0x00DA Write: POC:config
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
extern_offset_
correction
minislots_max
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-97. Protocol Configuration Register 29 (PCR29)
Base + 0x00DC Write: POC:config
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0
sync_node_max
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-98. Protocol Configuration Register 30 (PCR30)
Base + 0x0100 (MBCCSR0)
Base + 0x0108 (MBCCSR1)
...
Base + 0x04F8 (MBCCSR127)
Write: MCM, MBT, MTD: POC:config or MB_DIS
CMT: MB_LCK or MB_DIS
EDT, LCKT, MBIE, MBIF: Normal Mode
Additional Reset: CMT, DUP, DVAL, MBIF: Message Buffer Disable
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
MCM MBT MTD
CMT 0 0
MBIE
0 0 0 DUP DVAL EDS LCKS MBIF
W rwm EDT LCKT w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-99. Message Buffer Configuration, Control, Status Registers (MBCCSRn)