NXP Semiconductors PXN2020, Reference Manual, Page: 534 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-14 Freescale Semiconductor
24.3.2.5 eDMA Set Enable Request Register (EDMA_SERQR)
The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_ERQRL to enable the eDMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQ[0]) provides a global set
function, forcing the entire contents of EDMA_ERQRL to be asserted. Reads of this register return all
zeroes.
If bit 0 is set, the SERQ command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDM 0x0014 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EEI31 EEI30 EEI29 EEI28 EEI27 EEI26 EEI25 EEI24 EEI23 EEI22 EEI21 EEI20 EEI19 EEI18 EEI17 EEI16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-5. eDMA Enable Error Interrupt Register (EDMA_EEIRL)
Table 24-6. EDMA_EEIRL Field Descriptions
Field Description
EEIn Enable Error Interrupt n.
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generate an error interrupt request.
Offset: EDM 0x0018 Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP SERQ[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 24-6. eDMA Set Enable Request Register (EDMA_SERQR)