NXP Semiconductors PXN2020, Reference Manual, Page: 883 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-61
Figure 28-57. Time Base Period when Running in the Fastest Prescaler Ratio
Figure 28-58. Time Base Period when Running with a Prescaler Ratio Greater Than 1
Figure 28-59. Time Base Generation with External Clock and Clear on Match Start
When a match occurs, the first clock cycle is used to clear the internal counter,
starting another period. Note:
Prescaled Clock = 1
Internal Counter
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
Match Value = 3
Clock
See Note
PRESCALED CLOCK RATIO = 1 (Bypassed)
When a match occurs, the first clock cycle is used to clear the internal counter, and only
after a second edge of prescaled clock the counter will start counting. Note:
Prescaled Clock
Internal Counter
1 2 0
Match Value = 3
Clock
See Note
3 1 2 3 0 0 0
PRESCALED CLOCK RATIO = 3
System Clock
Input Event
Internal Counter
Match Value = 3
1 2 3 0
See Note
Note: When a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge
1 2
1 2 3 0
FLAG Set Event
FLAG Clear
FLAG Pin/Register
of prescaler clock enable the counter will start counting.