Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
28-59
28.4.2
IP Bus Interface Unit (BIU)
The BIU provides the interface between the internal interface bus (IIB) and the peripheral bus, allowing
communication among all submodules and this IP interface.
The BIU allows 8-, 16-, and 32-bit access. They are performed over a 32-bit data bus in a single cycle
clock.
28.4.2.1
Effect of Freeze on the BIU
When the FRZ bit in the EMIOS_MCR register is set and the module is in debug mode, the operation of
BIU is not affected.
28.4.3
Global Clock Prescaler Submodule (GCP)
The GCP divides the system clock to generate a clock for the CPs of the unified channels. It is a
programmable 8-bit up counter. The main clock signal is prescaled by the value defined in the GPRE bits
in EMIOS_MCR. The output is clocked every time the counter overflows. Counting is enabled by setting
the GPREN bit in the EMIOS_MCR. The counter can be stopped at any time by clearing this bit, thereby
stopping the internal counter in all the unified channels.
28.4.3.1
Effect of Freeze on the GCP
When the FRZ bit in the EMIOS_MCR register is set and the module is in debug mode, the operation of
GCP submodule is not affected, i.e., there is no freeze function in this submodule.
28.5
Reset
The eMIOS200 is reset by the global asynchronous system reset signal.
The MDIS bit in the EMIOS_MCR register and the UCDIS bits in the EMIOS_UCDIS registers are
cleared during reset.
On resetting the eMIOS200 all unified channels enter GPIO input mode.
28.6
Interrupts
The eMIOS200 can generate one interrupt per channel. An interrupt request is generated according to the
configuration of the channel and input events or matches. See
Chapter 10, Interrupts and Interrupt
for details on the eMIOS200 interrupt vector.
28.7
DMA Requests
The connection of the eMIOS200 DMA request signals to the DMA channel mux is described in
Section 23.5.2, Enabling and Configuring Sources.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
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Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
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