NXP Semiconductors PXN2020, Reference Manual, Page: 584 / 1376

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-18 Freescale Semiconductor
25.3.4.9 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB block.
This register is accessed by user software if there is a need to disable the MIB block operation. For
example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all
the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See
Table 25-3
for the locations of the MIB counters.
25.3.4.10 Receive Control Register (RCR)
The RCR is programmed by the user. The RCR controls the operational mode of the receive block and
1
Note: Observe maximum system clock frequency when programming MII_SPEED.
Offset: FE 0x0064 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MIB_
DISA
BLE
MIB_
IDLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-9. MIB Control Register (MIBC)
Table 25-12. MIBC Field Descriptions
Field Description
MIB_DISABLE A read/write control bit. If set, the MIB logic halts and does not update any MIB counters.
MIB_IDLE A read-only status bit. If set, the MIB block is not currently updating any MIB counters.