NXP Semiconductors PXN2020, Reference Manual, Page: 220 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-38 Freescale Semiconductor
8.3.2.21 General Purpose Register 0–3 (SIU_GPRn)
The SIU_GPR n registers provide general-purpose read/write registers for customer use.
8.3.2.22 System Clock Register (SIU_SYSCLK)
The SIU_SYSCLK register controls the source for the system clock, the divider for the system clock, and
eight fields that control the clock divider for groups of peripherals. For a listing of which peripherals are
associated with which LPCLKDIV bit on PXN20, see
Section 5.3.5, Peripheral Clock Dividers.
Offset: SI 0x0988 (SIU_GPR0)
0x098C (SIU_GPR1)
0x0990 (SIU_GPR2)
0x0994 (SIU_GPR3)
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
GP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-24. General Purpose Register 0–3 (SIU_GPRn)
Offset: SI 0x09A0 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SYSCLKSEL SYSCLKDIV
0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
LPCLKDIV3 LPCLKDIV2 LPCLKDIV1 LPCLKDIV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-25. System Clock Register (SIU_SYSCLK)