NXP Semiconductors PXN2020, Reference Manual, Page: 196 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-14 Freescale Semiconductor
8.3.2.2 Reset Status Register (SIU_RSR)
The SIU_RSR reflects the most recent source, or reset sources, and the pins’ configuration state at reset.
This register contains one bit for each reset source, indicating the last reset was power-on reset (POR),
external, software system, watchdog, loss of PLL lock, loss of clock, or checkstop reset. A reset status bit
set to logic one indicates the reset type that occurred. After it is set, the reset source status bits in the
SIU_RSR remain set until another reset occurs. In the following cases more than one reset bit is set:
1. If any reset request has negated and the device is still in the resulting reset, and then an external
reset is requested, both the original reset type and external reset status bits are set. In this case, the
device started the reset sequence due to due to a non-external reset request but ended the reset
sequence after an external reset request.
2. If any of the loss of clock, loss of lock, watchdog or checkstop reset requests occur on the same
clock cycle, and no other higher priority reset source is requesting reset ( Table 8-4 ), the reset status
bits for all of the requesting resets are set.
Simultaneous reset requests are prioritized. When reset requests of different priorities occur on the same
clock cycle, the lower priority reset request is ignored. Only the highest priority reset request's status bit is
set. Except for a power-on reset request and condition 1 above, all reset requests of any priority are ignored
until the device exits reset.
Table 8-4. Reset Source Priorities
Reset Source Priority
Power on reset (POR), LVI resets, and external reset (Group 0) Highest
Software system reset (Group1) .
Loss of clock, loss of lock, watchdog, checkstop (Group2) .
Software external reset (Group 3) Lowest
Offset: SI 0x000C Access: User read only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R PORS ERS LLRS LCRS WDRS CRS 0 0 0 0 0 0 0 0 SSRS 0
W
Reset
1
1
2
0
3
0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
BOOT
CFG
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U
4
0
1
The reset status register receives its reset values during power-on reset.
2
The PORS bit is also set on LVI or recovery from low-power sleep mode.
3
The ERS bit is also set if the RESET pin is held low to extend the reset sequence.
4
Before the rising edge of RESET, the PK9 pin state sets the BOOTCFG bit value. During sleep mode recovery, this
bit takes the state of PK9 when internal reset is negated.
Figure 8-3. Reset Status Register (SIU_RSR)