NXP Semiconductors PXN2020, Reference Manual, Page: 452 / 1376

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
18-12 Freescale Semiconductor
18.3.2.4.4 MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3)
The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the
region descriptor’s valid bit.
Because the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is
being updated because multiple writes are required to update the entire descriptor. Accordingly, the MPU
hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from
generating spurious access errors. In particular, it is expected that a complete update of a region descriptor
is typically done with sequential writes to MPU_RGD
n .Word0, then MPU_RGD n .Word1, ... and
MPU_RGD n .Word3. The MPU hardware automatically clears the valid bit on any writes to words {0,1,2}
of the descriptor. Writes to this word set/clear the valid bit in a normal manner.
Because it is also expected that system software may adjust the access controls within a region descriptor
(MPU_RGDn.Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is provided. If only the access controls are being updated, this operation must be performed by writing to
MPU_RGDAAC
n (alternate access control n ) as stores to these locations do not affect the descriptor’s
valid bit.
M0UM Bus Master ID 0 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 0 (e200z6)
when operating in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Offset: MP 0x400 + (16*n) + 0xc (MPU_RGDn.Word3) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PID PIDMASK
W
Reset – – – – – – – – – – – – – – – –
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-9. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3)
Table 18-8. MPU_RGDn.Word2 Field Descriptions (continued)
Field Description