NXP Semiconductors PXN2020, Reference Manual, Page: 312 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-44 Freescale Semiconductor
10.5.6 Selecting Priorities According to Request Rates and Deadlines
The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a
superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs which have higher request rates
have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is
assigned a priority according to the time from the request for the ISR to the deadline, not from the time of
the request for the ISR to the next request for it.
For example, ISR1 executes every 100

s, ISR2 executes every 200

s, and ISR3 executes every 300

s.
ISR1 has a higher priority than ISR2 which has a higher priority than ISR3; however, if ISR3 has a
deadline of 150

s, then it has a higher priority than ISR2.
The INTC has 16 priorities, which can be significantly fewer than the number of ISRs. In this case, group
the ISRs with other ISRs that have similar deadlines. For example, when a priority is allocated for every
time the request rate doubles, ISRs with request rates around 1 ms would share a priority, ISRs with request
rates around 500

s would share a priority, ISRs with request rates around 250

s would share a priority,
etc. With this approach, a range of ISR request rates of 2
16
could be covered, regardless of the number of
ISRs.
Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, it also
allows easier management of ISRs with similar deadlines that share a resource. They do not need to use
the PCP to access the shared resource.
10.5.7 Software Settable Interrupt Requests
The software settable interrupt requests can be used in two ways. They can be used to schedule a lower
priority portion of an ISR and for processors to interrupt other processors in a multiple processor system.
10.5.7.1 Scheduling a Lower Priority Portion of an ISR
A portion of an ISR needs to be executed at the PRI n value in INTC priority select registers
(INTC_PSR0–INTC_PSR315), which becomes the PRI value in INTC current priority register
(INTC_CPR_PRC0 or INTC_CPR_PRC1) with the interrupt acknowledge. The ISR, however, can have
a portion of it which does not need to be executed at this higher priority. Therefore, executing this later
portion that does not need to be executed at this higher priority can prevent the execution of ISRs that do
not have a higher priority than the earlier portion of the ISR but do have a higher priority than what the
later portion of the ISR needs. This preemptive scheduling inefficiency reduces the processor’s ability to
meet its deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule through the
RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount
H Interrupt exception handler epilog writes to INTC_EOIR.
I LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop from LIFO is the priority from
before peripheral interrupt request 100 interrupted. ISR108 now can access data block coherently after interrupt
exception handler executes rfi instruction.
Event Description