NXP Semiconductors PXN2020, Reference Manual, Page: 1194 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-44 Freescale Semiconductor
36.6.10.2.2 Ownership Trace Messaging (OTM)
Ownership trace information is messaged via the auxiliary port using an ownership trace message (OTM).
The e200z6 processor contains a Power Architecture Book E defined process ID register within the CPU.
The process ID register is updated by the operating system software to provide task/process ID
information. The contents of this register are replicated on the pins of the processor and connected to
Nexus. The process ID register value can be accessed using the
mfspr / mtspr instructions. Please refer to
the e200z6 Power Architecture
TM
Core Reference Manual for more details on the process ID register.
One condition causes an ownership trace message: When new information is updated in the OTR register
or process ID register by the e200z6 processor, the data is latched within Nexus, and is messaged out via
the auxiliary port, allowing development tools to trace ownership flow.
Ownership trace information is messaged out in the following format:
Figure 36-26. Ownership Trace Message Format
36.6.10.2.3 OTM Error Messages
An error message occurs when a new message cannot be queued due to the message queue being full. The
FIFO discards incoming messages until it has completely emptied the queue. Once emptied, an error
message is queued. The error encoding indicates which types of messages attempted to be queued while
the FIFO was being emptied.
If only an OTM message attempts to enter the queue while it is being emptied, the error message
incorporates the OTM only error encoding (00000). If both OTM and either BTM or DTM messages
attempt to enter the queue, the error message incorporates the OTM and (program or data) trace error
encoding (00111). If a watchpoint also attempts to be queued while the FIFO is being emptied, then the
error message incorporates error encoding (01000).
NOTE
The OVC bits within the DC1 register can be set to delay the CPU in order
to alleviate (but not eliminate) potential overrun situations.
Error information is messaged out in the following format (see Table 36-15 )
Figure 36-27. Error Message Format
PROCESS
MSB LSB
1 2
SRC TCODE (000010)
3
6 bits 4 bits 32 bits
Fixed length = 42 bits
ECODE (00000 / 00111 / 01000)
MSB LSB
1 2
SRC TCODE (001000)
3
6 bits 4 bits 5 bits
Fixed length = 15 bits