NXP Semiconductors PXN2020, Reference Manual, Page: 468 / 1376

Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
19-8 Freescale Semiconductor
Table 19-6. EEGR Field Descriptions
Field Description
FRC1BI Force Platform RAM Continuous 1-Bit Data Inversions. The assertion of this bit forces the platform RAM controller
to create 1-bit data inversions, as defined by the bit position specified in ERRBIT[6:0], continuously on every write
operation.
The normal ECC generation takes place in the PRAM controller, but then the polarity of the bit position defined by
ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
0 No platform RAM continuous 1-bit data inversions are generated.
1 1-bit data inversions in the platform RAM are continuously generated.
FR11BI Force Platform RAM One 1-bit Data Inversion. The assertion of this bit forces the platform RAM controller to create
one 1-bit data inversion, as defined by the bit position specified in ERRBIT[6:0], on the first write operation after this
bit is set. The normal ECC generation takes place in the PRAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again
to properly re-enable the error generation logic.
0 No platform RAM single 1-bit data inversion is generated.
1 One 1-bit data inversion in the platform RAM is generated.
FRCNCI Force Platform RAM Continuous Noncorrectable Data Inversions. The assertion of this bit forces the platform RAM
controller to create 2-bit data inversions, as defined by the bit position specified in ERRBIT and the overall odd
parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous noncorrectable data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the PRAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
0 No platform RAM continuous 2-bit data inversions are generated.
1 2-bit data inversions in the platform RAM are continuously generated.
FR1NCI Force Platform RAM One Noncorrectable Data Inversions. The assertion of this bit forces the platform RAM
controller to create one 2-bit data inversion, as defined by the bit position specified in ERRBIT and the overall odd
parity bit, on the first write operation after this bit is set.
The normal ECC generation takes place in the PRAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly
re-enable the error generation logic.
0 No platform RAM single 2-bit data inversions are generated.
1 One 2-bit data inversion in the platform RAM is generated.