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NXP Semiconductors PXN2020 Reference Manual Download Page 591

Fast Ethernet Controller (FEC)

PXN20 Microcontroller Reference Manual, Rev. 1

Freescale Semiconductor

25-25

25.3.4.18 Descriptor Group Lower Address (GALR)

The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table 
used in the address recognition process for receive frames with a multicast address. This register must be 
initialized by the user.

25.3.4.19  FIFO Transmit FIFO Watermark Register (TFWR)

The TFWR is a 32-bit read/write register with one 2-bit field programmed by the user to control the 
amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the 
user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due 
to contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO 
underrun due to contention for the system bus. The byte counts associated with the TFWR field may need 
to be modified to match a given system requirement (worst case bus access latency by the transmit data 
DMA channel).

Table 25-20. GAUR Field Descriptions

Field

Description

GADDR1

The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition 
process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of 
GADDR1 contains hash index bit 32.

Offset: FE 0x0124 

Access: User read/write

 

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R

GADDR2

W

Reset

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

R

GADDR2

W

Reset

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

Figure 25-19. Descriptor Group Lower Address Register (GALR)

Table 25-21. GALR Field Descriptions

Field

Description

GADDR2

The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition 
process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of 
GADDR2 contains hash index bit 0.

Summary of Contents for PXN2020

Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...

Page 2: ...ity arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters...

Page 3: ...ommunications Module I2C 1 13 1 7 12 Serial Peripheral Interface Module SPI 1 13 1 7 13 Enhanced Modular Input Output System Timers eMIOS200 1 14 1 7 14 Periodic Interrupt Timer Module PIT 1 14 1 7 15...

Page 4: ...10 PC10 GPIO PC 10 Analog Input AN 42 FlexRay Debug 0 FR_DBG 0 3 24 3 4 3 11 PC11 GPIO PC 11 Analog Input AN 43 I2 C_C Serial Clock Line SCL_C 3 24 3 4 3 12 PC12 GPIO PC 12 Analog Input AN 44 I2 C_C S...

Page 5: ...a Output SOUT_D 3 30 3 4 6 15 PF14 GPIO PF 14 DSPI_D Data Input SIN_D 3 31 3 4 6 16 PF15 GPIO PF 15 DSPI_D Peripheral Chip Select PCS_D 0 DSPI_A Peripheral Chip Select PCS_A 5 DSPI_B Peripheral Chip S...

Page 6: ...J8 GPIO PJ 8 eMIOS Channel eMIOS 7 3 36 3 4 9 10 PJ9 GPIO PJ 9 eMIOS Channel eMIOS 6 3 36 3 4 9 11 PJ10 GPIO PJ 10 eMIOS Channel eMIOS 5 3 36 3 4 9 12 PJ11 GPIO PJ 11 eMIOS Channel eMIOS 4 3 36 3 4 9...

Page 7: ...l Clock Input EXTAL 3 41 3 4 14 2 Crystal Oscillator Output XTAL 3 41 3 4 14 3 System Clock Output CLKOUT 3 41 3 4 15 Power Ground Signals 3 41 3 4 15 1 Internal Logic Supply Input VDD 3 41 3 4 15 2 F...

Page 8: ...z XTAL 5 3 5 1 3 1 4 40 MHz XTAL Features 5 3 5 1 4 Internal High Frequency RC Oscillator 16 MHz_IRC 5 4 5 1 4 1 16 MHz_IRC Features 5 4 5 1 5 Internal Low Frequency RC Oscillator 128 kHz_IRC 5 4 5 1...

Page 9: ...17 6 3 3 Low Power Mode Entry 6 18 6 3 3 1 CRP Clock Selection 6 18 6 3 3 2 Sleep Mode RAM Retention 6 19 6 3 4 Low Power Operation 6 19 6 3 4 1 Sleep Mode Reset Operation 6 23 6 3 5 Low Power Wakeup...

Page 10: ...SIU_PCR 8 22 8 3 2 14 GPIO Pin Data Output Registers SIU_GPDO16_19 SIU_GPDO152_154 8 26 8 3 2 15 GPIO Pin Data Input Registers SIU_GPDI0_3 SIU_GPDI152_154 8 28 8 3 2 16 IMUX Select Register 1 SIU_ISE...

Page 11: ..._B SIU_EMIOSB 8 64 8 3 2 57 SIU_DSPIBH L Select Register for DSPI_B SIU_DSPIAHLB 8 64 8 3 2 58 eMIOS Select Register for DSPI_C SIU_EMIOSC 8 65 8 3 2 59 SIU_DSPICH L Select Register for DSPI_C SIU_DSP...

Page 12: ...Vector Mode Handshaking 10 36 10 4 3 2 Hardware Vector Mode Handshaking 10 37 10 5 Initialization Application Information 10 38 10 5 1 Initialization Flow 10 38 10 5 2 Interrupt Exception Handler 10...

Page 13: ...Space Block Select Register HBS 12 15 12 3 2 7 Address Register ADR 12 16 12 3 2 8 Platform Flash Configuration Register for Port n PFCRPn 12 17 12 3 2 9 Platform Flash Access Protection Register PFAP...

Page 14: ...cement Algorithm 13 25 13 3 2 4 Cache Power Reduction 13 25 13 3 2 5 L1 Cache Control and Status Register 0 L1CSR0 13 25 13 3 2 6 L1 Cache Configuration Register 0 L1CFG0 13 28 13 3 3 Interrupt Types...

Page 15: ...ch AXBS 16 1 Introduction 16 1 16 1 1 Block Diagram 16 1 16 1 2 AXBS Controller Configuration 16 1 16 1 3 Overview 16 2 16 1 4 Features 16 2 16 1 5 Modes of Operation 16 3 16 1 5 1 Normal Mode 16 3 16...

Page 16: ...1 19 2 1 Module Memory Map 19 2 19 2 2 Register Descriptions 19 3 19 2 2 1 FEC Burst Optimization Master Control Register FBOMCR 19 3 19 2 2 2 ECC Configuration Register ECR 19 5 19 2 2 3 ECC Status...

Page 17: ...of Operation 22 2 22 2 Signal Description 22 2 22 2 1 External Signal Description 22 2 22 3 Memory Map and Registers 22 2 22 3 1 Module Memory Map 22 2 22 3 2 Register Descriptions 22 4 22 3 2 1 PIT...

Page 18: ...MA_CEEIR 24 16 24 3 2 9 eDMA Clear Interrupt Request Register EDMA_CIRQR 24 17 24 3 2 10 eDMA Clear Error Register EDMA_CER 24 18 24 3 2 11 eDMA Set START Bit Register EDMA_SSBR 24 18 24 3 2 12 eDMA C...

Page 19: ...13 Physical Address Upper Register PAUR 25 21 25 3 4 14 Opcode Pause Duration Register OPD 25 22 25 3 4 15 Descriptor Individual Upper Address Register IAUR 25 23 25 3 4 16 Descriptor Individual Lowe...

Page 20: ...r MVR 26 13 26 5 2 4 Module Configuration Register MCR 26 14 26 5 2 5 System Memory Base Address Register SYMBADR 26 15 26 5 2 6 Strobe Signal Control Register STBSCR 26 16 26 5 2 7 Message Buffer Dat...

Page 21: ...nd POP Count Register RFFLPCR 26 60 26 5 2 59 Receive FIFO Message ID Acceptance Filter Value Register RFMIDAFVR 26 61 26 5 2 60 Receive FIFO Message ID Acceptance Filter Mask Register RFMIAFMR 26 61...

Page 22: ...onization 26 134 26 6 12Sync Frame ID and Sync Frame Deviation Tables 26 135 26 6 12 1 Sync Frame ID Table Content 26 136 26 6 12 2 Sync Frame Deviation Table Content 26 136 26 6 12 3 Sync Frame ID an...

Page 23: ...s Configuration Register SBCR 27 14 27 3 2 7 Asynchronous Base Address Configuration Register ABCR 27 14 27 3 2 8 Control Base Address Configuration Register CBCR 27 15 27 3 2 9 Isochronous Base Addre...

Page 24: ...200 Control Register EMIOS_CCR n 28 14 28 3 2 9 eMIOS200 Status Register EMIOS_CSR n 28 19 28 3 2 10 eMIOS200 Alternate A Register EMIOS_ALTA n 28 20 28 4 Functional Description 28 20 28 4 1 Unified C...

Page 25: ...ed Features 29 35 29 4 7 1 Remote Frames 29 35 29 4 7 2 Overload Frames 29 35 29 4 7 3 Time Stamp 29 35 29 4 7 4 Protocol Timing 29 36 29 4 7 5 Arbitration and Matching Timing 29 38 29 4 8 Modes of Op...

Page 26: ...zation 30 36 30 4 4 5 DSI Transfer Initiation Control 30 37 30 4 5 Combined Serial Interface CSI Configuration 30 37 30 4 5 1 CSI Serialization 30 38 30 4 5 2 CSI Deserialization 30 39 30 4 6 Buffered...

Page 27: ...eSCI_CR2 31 8 31 3 2 4 eSCI Data Register eSCI_DR 31 10 31 3 2 5 eSCI Interrupt Flag and Status Register 1 eSCI_IFSR1 31 11 31 3 2 6 eSCI Interrupt Flag and Status Register 2 eSCI_IFSR2 31 12 31 3 2 7...

Page 28: ...pt Configuration Register IBIC 32 11 32 4 Functional Description 32 11 32 4 1 I Bus Protocol 32 11 32 4 1 1 START Signal 32 12 32 4 1 2 Slave Address Transmission 32 13 32 4 1 3 Data Transfer 32 13 32...

Page 29: ...WTISR 34 16 34 3 2 12 Watchdog Threshold Interrupt Mask Register WTIMR 34 17 34 3 2 13 DMA Enable Register DMAE 34 18 34 3 2 14 DMA Channel Select Register 0 DMAR0 34 18 34 3 2 15 DMA Channel Select...

Page 30: ...ss Mode 35 4 35 1 3 4 TAP Sharing Mode 35 4 35 2 External Signal Description 35 5 35 3 Memory Map and Registers 35 5 35 3 1 Instruction Register 35 5 35 3 2 Bypass Register 35 5 35 3 3 Device Identifi...

Page 31: ...nctional Description 36 18 36 5 5 1 NPC Reset Configuration 36 18 36 5 5 2 Auxiliary Output Port 36 18 36 5 6 NPC Initialization Application Information 36 23 36 6 e200z6 Class 3 Nexus Module Nexus3 3...

Page 32: ...te Access Data RWD 36 80 36 7 7 6 Watchpoint Trigger Register WT 36 81 36 7 8 Nexus2 Register Access via JTAG OnCE 36 82 36 7 9 Nexus2 Functional Description 36 83 36 7 9 1 Debug Status Messages 36 83...

Page 33: ...principles of software and hardware and basic details of the Power Architecture Organization This document includes chapters that describe The microcontroller as a whole The functionality of the indi...

Page 34: ...e200z6 Power processor core and gives an overview of the programming models as they are implemented on the device The e200z6 is the main processor core on the PXN20 Chapter 14 e200z0 Core Z0 describes...

Page 35: ...eSCI interface which allows asynchronous serial communications with off chip peripheral devices Chapter 32 Inter Integrated Circuit Bus Controller Module I2C describes the I2 C module including I2 C...

Page 36: ...nce manuals Because some processors have follow on parts an addendum is provided that describes the additional features and functionality changes Also if mistakes are found within a reference manual a...

Page 37: ...such as signal encodings x without italics indicates a don t care condition x With italics used to express an undefined alphanumeric value e g a variable in an equation or a variable alphabetic chara...

Page 38: ...LDNAME Indicates a read only bit field in a memory mapped register W R Indicates a write only bit field in a memory mapped register W FIELDNAME R FIELDNAME Write 1 to clear indicates that writing a 1...

Page 39: ...t significant byte msb Most significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PLIC Physical layer interface controller PLL Phase locked loop POR Power on...

Page 40: ...n word of the instruction ea Effective address ea y ea x Source and destination effective addresses respectively label Assembly language program label list List of registers for MOVEM instruction exam...

Page 41: ...fter then are performed If the condition is false and the optional else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs...

Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...

Page 43: ...and an operating system to assist with user implementations The PXN20 devices have two levels of memory hierarchy a 32 KB unified cache and 2 MB of internal flash The PXN20 has 128 KB on chip L2 SRAM...

Page 44: ...nels 16 bit 32 channels 16 bit Cross Trigger Unit CTU No Yes Asynchronous Serial Interfaces UART 6 12 Synchronous Serial Interfaces SPI 4 4 Controller Area Network CAN Controller 6 5 Inter Integrated...

Page 45: ...FlexRay VREG Controller SWT STM RTC API INTC PIT BAM SIU ADC Analog to digital converter BAM Boot assist module CAN Controller area network controller ECC Error correction code ECSM Error correction s...

Page 46: ...CC Flash ECC CTU Debug MPU Memory protection unit NDI Nexus debug interface PBRIDGE Peripheral I O bridge PIT Periodic interrupt timer RTC Real time clock SIU System integration unit SPI Serial periph...

Page 47: ...clock gating to halt the clock for all or part of the device The lowest power mode also uses power gating to automatically turn off the power supply to parts of the device to minimize leakage Dynamic...

Page 48: ...ine for emulation providing access to full Nexus port without sacrificing GPIO functionality not available for production 1 7 Module Features The following sections provide details of the modules impl...

Page 49: ...ent code size footprint Minimizes impact on performance Branch processing acceleration using lookahead instruction buffer Load store unit 1 cycle load latency Misaligned access support No load to use...

Page 50: ...tes erase and verify sequence Supports flash writes using internal 16 MHz RC oscillator Flash partitioning Error correction status Configurable error correcting codes ECC reporting for RAM and flash T...

Page 51: ...lator includes the following features Single supply device 3 3 V 5 V nominal input supply voltage supported Supports I O levels independent of main supply MLB has separate supply pins to support down...

Page 52: ...rnally multiplexed channels Internal control to support generation of external analog multiplexor selection Four internal channels optionally used to support externally multiplex inputs providing tran...

Page 53: ...mbination of 64 input flags events connected to different timers in the system Maskable interrupt generation whenever a trigger output is generated Event configuration registers dedicated to UC flag t...

Page 54: ...t driven operation with 16 interrupt sources LIN slave mode features Autonomous LIN header handling Autonomous LIN response handling Discarding of irrelevant LIN responses using up to 16 ID filters 1...

Page 55: ...nal generation Acknowledge bit generation detection Bus busy detection 1 7 12 Serial Peripheral Interface Module SPI The PXN20 SPI features the following Full duplex synchronous transfers Master or sl...

Page 56: ...offering input capture and output compare functions Up to 32 1 dual action channels offering output pulse width modulation Up to 13 1 output pulse width and frequency modulation and center aligned out...

Page 57: ...otential request sources 1 7 17 Crossbar Switch XBAR The Crossbar Switch allows concurrent accesses between masters and slaves and provides these features Up to 6 master ports Masters Z6 CPU Z0 CPU eD...

Page 58: ...he PXN20 System clock can be derived from the following sources 4 40 MHz XTAL FMPLL 16 MHz IRC oscillator Programmable output clock divider of system clock 1 2 4 Separate programmable peripheral bus c...

Page 59: ...utput pins The exception is selected precision ADC channels which support alternative configuration as general purpose inputs only Direct readback of the pin value supported on all digital output pins...

Page 60: ...tion can lock multiple buffers at the same time Message buffers can be configured as Receive message buffer Single buffered transmit message buffer Double buffered transmit message buffer combines two...

Page 61: ...7 26 Real Time Counter RTC Real Time counter supports wake up from Low Power modes or real time clock generation Configurable resolution for different timeout periods 1 sec resolution for 1 hour peri...

Page 62: ...via branch trace messaging BTM Data trace via data write messaging DWM and data read messaging DRM This allows the development tools to trace reads and or writes to selected internal memory resources...

Page 63: ...or 1 21 Nexus supports debug through reset and low power 1 8 Developer Support This family of MCUs is supported by Freescale s Tower Development System as well as a broad set of advanced debug and run...

Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...

Page 65: ...001_3FFF 16 Program Data Flash LAS Block L4 0x0001_4000 0x0001_7FFF 16 Program Data Flash LAS Block L5 0x0001_8000 0x0001_BFFF 16 Program Data Flash LAS Block L6 0x0001_C000 0x0001_FFFF 16 Program Dat...

Page 66: ...496 Reserved 0xC3F8_0000 0xC3F8_3FFF 16 Reserved 0xC3F8_4000 0xC3F8_7FFF 16 MLB_DIM Configuration X 0xC3F8_8000 0xC3F8_BFFF 16 I2C_C 0xC3F8_C000 0xC3F8_FFFF 16 I2C_D 0xC3F9_0000 0xC3F9_3FFF 16 DSPI_C...

Page 67: ...d 0xFFF0_4000 0xFFF0_7FFF 16 AXBS 0xFFF0_8000 0xFFF0_FFFF 32 Reserved 0xFFF1_0000 0xFFF1_3FFF 16 Sema4 0xFFF1_4000 0xFFF1_7FFF 16 MPU X 0xFFF1_8000 0xFFF3_7FFF 128 Reserved 0xFFF3_8000 0xFFF3_BFFF 16...

Page 68: ...FC_7FFF 16 FlexCan_B 0xFFFC_8000 0xFFFC_BFFF 16 FlexCan_C 0xFFFC_C000 0xFFFC_FFFF 16 FlexCan_D 0xFFFD_0000 0xFFFD_3FFF 16 FlexCan_E 0xFFFD_4000 0xFFFD_7FFF 16 FlexCan_F X 0xFFFD_8000 0xFFFD_BFFF 16 CT...

Page 69: ...e 3 1 shows the signals properties for each pin on PXN20 For all port pins that have an associated SIU_PCRn register to control pin properties the supported functions column lists the functions associ...

Page 70: ...og Input I I VDDA IHA E15 PA2 PA 2 AN 2 2 00 01 10 11 Port A GPI ADC Analog Input I I VDDA IHA F16 PA3 PA 3 AN 3 3 00 01 10 11 Port A GPI ADC Analog Input I I VDDA IHA F15 PA4 PA 4 AN 4 4 00 01 10 11...

Page 71: ...I I VDDA IHA D16 PA15 PA 15 AN 15 XTAL32 15 00 01 10 11 Port A GPI ADC Analog Input External 32 kHz Crystal Out I I O VDDA IHA E16 Port B 16 PB0 PB 0 AN 16 ANW 16 00 01 10 11 Port B GPIO ADC Analog In...

Page 72: ...t I O I O VDDE1 SHA B12 PB10 PB 10 AN 26 PCS_B 4 26 00 01 10 11 Port B GPIO ADC Analog Input DSPI_B Peripheral Chip Select I O I O VDDE1 SHA A9 PB11 PB 11 AN 27 PCS_B 5 27 00 01 10 11 Port B GPIO ADC...

Page 73: ...s Event Out I O I O VDDE1 SHA B7 PC4 PC 4 AN 36 36 00 01 10 11 Port C GPIO ADC Analog Input I O I VDDE1 SHA D8 PC5 PC 5 AN 37 Z6NMI 37 00 01 10 11 Port C GPIO ADC Analog Input Z6 Core Non Maskable Int...

Page 74: ...Port C GPIO ADC Analog Input ADC Ext Mux Address Select I O I O VDDE1 SHA C5 PC14 PC 14 AN 46 MA 1 46 00 01 10 11 Port C GPIO ADC Analog Input ADC Ext Mux Address Select I O I O VDDE1 SHA C4 PC15 PC...

Page 75: ...Port D GPIO FlexCAN_E Transmit SCI_L Transmit I2C_C Serial Clock I O O O I O VDDE2 SH E2 PD9 PD 9 CNRX_E RXD_L SDA_C 57 00 01 10 11 Port D GPIO FlexCAN_E Receive SCI_L Receive I2 C_C Serial Data I O I...

Page 76: ...annel I O O I O VDDE2 SH F4 PE3 PE 3 RXD_D eMIOS 28 67 00 01 10 11 Port E GPIO eSCI_D Receive eMIOS Channel I O I I O VDDE2 SH F3 PE4 PE 4 TXD_E eMIOS 27 68 00 01 10 11 Port E GPIO eSCI_E Transmit eMI...

Page 77: ...PIO eSCI_J Transmit DSPI_C Peripheral Chip Select I O O O VDDE2 SH P4 PE13 PE 13 RXD_J PCS_C 3 77 00 01 10 11 Port E GPIO eSCI_J Receive DSPI_C Peripheral Chip Select I O I O VDDE2 SH P5 PE14 PE 14 SC...

Page 78: ..._A Peripheral Chip Select DSPI_C Peripheral Chip Select I O I O O VDDE2 SH N1 PF7 PF 7 PCS_B 0 PCS_C 5 PCS_D 4 87 00 01 10 11 Port F GPIO DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select DS...

Page 79: ...DE2 SHA A3 PG2 PG 2 PCS_D 1 SCL_C AN 50 98 00 01 10 11 Port G GPIO DSPI_D Peripheral Chip Select I2 C_C Serial Clock ADC Analog Input I O O I O I VDDE3 SHA H14 PG3 PG 3 PCS_D 2 SDA_C AN 51 99 00 01 10...

Page 80: ...thernet Receive Clock ADC Analog Input I O I O I I VDDE3 SHA J16 PG12 PG 12 eMIOS 3 FEC_TXD 0 AN 60 108 00 01 10 11 Port G GPIO eMIOS Channel Ethernet Transmit Data ADC Analog Input I O I O O I VDDE3...

Page 81: ...GPIO eMIOS Channel Ethernet Receive Data I O I O I VDDE3 SH R14 PH6 PH 6 eMIOS 25 FEC_RXD 2 118 00 01 10 11 Port H GPIO eMIOS Channel Ethernet Receive Data I O I O I VDDE3 SH R15 PH7 PH 7 eMIOS 24 FEC...

Page 82: ..._A 5 129 00 01 10 11 Port J GPIO eMIOS Channel DSPI_A Peripheral Chip Select I O I O O VDDE4 SH T7 PJ2 PJ 2 eMIOS 13 PCS_B 1 130 00 01 10 11 Port J GPIO eMIOS Channel DSPI_B Peripheral Chip Select I O...

Page 83: ...PJ10 PJ 10 eMIOS 05 138 00 01 10 11 Port J GPIO eMIOS Channel I O I O VDDE4 SH N12 PJ11 PJ 11 eMIOS 04 139 00 01 10 11 Port J GPIO eMIOS Channel I O I O VDDE4 SH P12 PJ12 PJ 12 eMIOS 03 140 00 01 10...

Page 84: ...PK5 PK 5 FR_A_TX_EN MA 2 PCS_C 3 149 00 01 10 11 Port K GPIO FlexRay A Transmit Enable ADC Ext Mux Address Select DSPI_C Peripheral Chip Select I O O O O VDDE2 MH T4 PK6 PK 6 FR_B_RX PCS_B 1 PCS_C 4...

Page 85: ...in the SIU_PCRn register selects the signal function for the pin A dash in the Description field of this table indicates that this value for PC is reserved on this pin and should not be used 5 The pad...

Page 86: ...VDDE3 J13 J13 VDDE4 N10 N10 VDDA Analog Power 3 3 or 5 0 V B15 B15 VDD33 3 3 V I O Power 3 3 V L13 L13 VDDEMLB Media Local Bus Power 2 5 or 3 3 V K4 K4 VDDENEX 2 2 Dedicated Nexus power pin on 256 pi...

Page 87: ...PD8 G VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PE6 H VSS VSS VSS VSS PE9 PD14 J PD15 PE0 K PE1 L M VSS PF0 VSS N PG3 PF1 EXTAL P PG5 PF2 TDI R VDD PG6 T A B C D E F G H J K L M 1 2 3 4 5 6 7 8...

Page 88: ...D13 PD12 PE7 PA4 PA0 XTAL TMS PC6 PD5 PE2 VSSSYN PJ2 PA2 PJ13 PJ14 PJ15 PJ12 PH5 PH6 PH7 PJ8 PJ9 VDDE2 PH0 PH2 PG13 PG14 PG9 PG10 PG11 PG0 PJ4 PF7 PF11 PJ6 PG2 PF13 PJ3 PJ7 PF10 PG1 PF4 PF9 PJ5 TDO VD...

Page 89: ...15 GPI PA 15 Analog Input AN 15 32 kHz Crystal Output XTAL32 PA 15 is a GPI pin AN 15 is a single ended analog input pin XTAL32 is the output pin for an external 32 kHz crystal oscillator 3 4 2 Port B...

Page 90: ...is a GPIO pin AN 25 is a single ended analog input pin PCS_A 3 is a peripheral chip select output pin for the DSPI A module 3 4 2 8 PB10 GPIO PB 10 Analog Input AN 26 DSPI_B Peripheral Chip Select PCS...

Page 91: ...s a GPIO pin AN 34 is a single ended analog input pin EVTI is the Nexus Event Input pin 3 4 3 3 PC3 GPIO PC 3 Analog Input AN 35 Nexus Event Out EVTO PC 3 is a GPIO pin AN 35 is a single ended analog...

Page 92: ...C_C module 3 4 3 12 PC12 GPIO PC 12 Analog Input AN 44 I2C_C Serial Data Line SDA_C PC 12 is a GPIO pin AN 44 is a single ended analog input pin SDA_C is the serial data line for the I2 C_B module 3 4...

Page 93: ...3 4 4 6 PD5 GPIO PD 5 CAN_C Receive CNRX_C PD 5 is a GPIO pin CNRX_C is the receive input pin for the FlexCAN C module PD 5 can be configured as a wakeup pin in the CRP_PWKENL register 3 4 4 7 PD6 GPI...

Page 94: ...he FlexCAN F module RXD_M is the receive input pin for the eSCI M module SDA_D is the serial data line for the I2 C D module PD 11 can be configured as a wakeup pin in the CRP_PWKENL register 3 4 4 13...

Page 95: ...as a wakeup pin in the CRP_PWKENL register 3 4 5 5 PE4 GPIO PE 4 eSCI_E Transmit TXD_E eMIOS Channel eMIOS 27 PE 4 is a GPIO pin TXD_E is the transmit output pin for the eSCI E module eMIOS 27 is an...

Page 96: ...PE11 GPIO PE 11 eSCI_H Receive RXD_H DSPI_B Peripheral Chip Select PCS_B 2 PE 11 is a GPIO pin RXD_H is the receive input pin for the eSCI H module PCS_B 2 is a peripheral chip select output pin for...

Page 97: ...I_C Peripheral Chip Select PCS_C 4 PF 3 is a GPIO pin PCS_A 0 is a peripheral chip select input output pin for the DSPI A module PCS_B 5 is a peripheral chip select output pin for the DSPI B module PC...

Page 98: ..._PWKENH register 3 4 6 9 PF8 GPIO PF 8 DSPI_C Clock SCK_C PF 8 is a GPIO pin SCK_C is the SPI clock pin for the DSPI C module 3 4 6 10 PF9 GPIO PF 9 DSPI_C Data Output SOUT_C PF 9 is a GPIO pin SOUT_C...

Page 99: ...7 2 PG1 GPIO PG 1 DSPI_A Peripheral Chip Select PCS_A 5 DSPI_B Peripheral Chip Select PCS_B 4 Analog Input AN 49 PG 1 is a GPIO pin PCS_A 5 is a peripheral chip select output pin for the DSPI A modul...

Page 100: ...AN 56 PG 8 is a GPIO pin eMIOS 7 is an input output channel pin for the eMIOS200 module FEC_TX_CLK is the Ethernet transmit clock input pin AN 56 is a single ended analog input pin 3 4 7 10 PG9 GPIO...

Page 101: ...hannel pin for the eMIOS200 module FEC_TXD 3 is an Ethernet transmit data output pin AN 63 is a single ended analog input pin 3 4 8 Port H Pins 3 4 8 1 PH0 GPIO PH 0 eMIOS Channel eMIOS 31 Ethernet Co...

Page 102: ...IOS 24 Ethernet Receive Data FEC_RXD 3 PH 7 is a GPIO pin eMIOS 24 is an input output channel pin for the eMIOS200 module FEC_RXD 3 is an Ethernet receive data input pin 3 4 8 9 PH8 GPIO PH 8 eMIOS Ch...

Page 103: ...ipheral chip select output pin for the DSPI A module 3 4 9 3 PJ2 GPIO PJ 2 eMIOS Channel eMIOS 13 DSPI_B Peripheral Chip Select PCS_B 1 PJ 2 is a GPIO pin eMIOS 13 is an input output channel pin for t...

Page 104: ...IOS200 module PJ 9 can be configured as a wakeup pin in the CRP_PWKENH register 3 4 9 11 PJ10 GPIO PJ 10 eMIOS Channel eMIOS 5 PJ 10 is a GPIO pin eMIOS 5 is an input output channel pin for the eMIOS2...

Page 105: ...Input SIN_B DSPI_D Peripheral Chip Select PCS_D 5 PK 2 is a GPIO pin MLBDAT is the bidirectional data line that transfers user data to from the MOST network controller SIN_B is the data input pin for...

Page 106: ...PK7 GPIO PK 7 FlexRay Channel B Transmit FR_B_TX DSPI_B Peripheral Chip Select PCS_B 2 DSPI_C Peripheral Chip Select PCS_C 5 PK 7 is a GPIO pin FR_B_TX is the FlexRay Channel B transmit pin PCS_B 2 i...

Page 107: ...trace After reset the EVTI pin is used to initiate program and data trace synchronization messages or generate a breakpoint On the 208 pin BGA package this pin is multiplexed with PC2 3 4 11 2 Nexus...

Page 108: ...4 13 JTAG Signals For more information see Chapter 35 IEEE 1149 1 Test Access Port Controller JTAGC 3 4 13 1 JTAG Test Clock Input TCK TCK provides the clock input for the on chip test logic 3 4 13 2...

Page 109: ...output This signal is multiplexed with PK9 user mode and PK0 test mode 3 4 15 Power Ground Signals 3 4 15 1 Internal Logic Supply Input VDD VDD is the 1 2 V nominal internal logic supply input 3 4 15...

Page 110: ...s the 3 3 V or 5 V nominal input power supply 3 4 15 9 Voltage Regulator Control Output VRCCTL VRCCTL is the current control for external NPN transistor 3 4 15 10 Supply VRCSEL VRCSEL is the input pow...

Page 111: ...ge of 0 18V 1 A per per for a differential voltage of 0 27V 5 A per pin for a differential voltage of 0 33V up to 300 A per pin for a differential voltage of 0 5V If the internal pull devices are enab...

Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...

Page 113: ...al logic and controls the assertion of the RESET pin The MCU is clocked by the 16 MHz IRC clock after any reset The reset status register SIU_RSR gives the source or sources of the last reset and is u...

Page 114: ...s set 4 2 2 Boot Configuration BOOTCFG The BOOTCFG pin pin name PK9 in package diagrams and signal lists is used to determine the boot mode initiated by the BAM program The pin state during reset is l...

Page 115: ...loss of lock reset occurs when the PLL loses lock and the loss of lock reset enable LOLRE bit in the PLL enhanced synthesizer control register 2 ESYNCR2 is set The internal reset signal and RESET pin...

Page 116: ..._RSR are cleared 4 4 Reset Configuration The reset state of the system is All pads on ports A K are placed in a disabled mode with output enables input enables and pull devices all disabled PK9 is con...

Page 117: ...uming VDD and VDD33 are within valid operating ranges The value of the BOOTCFG pin is latched 4 clock cycles before the negation of the RESET pin and stored in the reset status register Figure 4 1 Res...

Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...

Page 119: ...equency RC Oscillator 128 kHz_IRC This is mainly used as an independent clock source for the ultra low power modes 32 kHz crystal oscillator described in Section 5 1 6 External Low Frequency Crystal 3...

Page 120: ...ck for rapid start up from low power modes Provides a back up clock in the event of PLL or external oscillator clock failure Provides watchdog timer 5 accuracy over the operating temperature range aft...

Page 121: ...be kept enabled in Sleep mode to facilitate fast start up In this mode the crystal oscillator cannot drive any internal modules e g RTC API as the output driver is disabled 5 1 3 1 4 40 MHz XTAL Featu...

Page 122: ...MHz_IRC is the default system clock out of reset This clock features the following Clock for rapid startup from low power modes Can be configured to run in Sleep mode Backup clock in case of external...

Page 123: ...he 32 kHz_XTAL clock is an external low power high accuracy clock source to provide the optional clock source for the RTC API 5 1 6 1 32 kHz_XTAL Features Two external pins required EXTAL32 and XTAL32...

Page 124: ...nal indicating the FMPLL has acquired lock and continuously monitors the FMPLL output for any loss of lock Loss of clock circuitry monitors input reference and FMPLL output clocks with programmable ab...

Page 125: ...FMPLL 32_kHz_XTAL 128_kHz_IRC 1 to 1 Dividers 1 2 4 8 16 2 Dividers 1 2 4 8 3 Dividers 1 2 4 1 to 82 1 to 82 2 PLL_Clk 116 MHz 4 40_MHz_XTAL 16_MHZ_IRC Peripheral Set 1 Core Platform Peripheral Set 2...

Page 126: ...source divided by 1 2 4 8 or 16 based on the setting of the SYSCLKDIV field in the SIU system clock register SIU_SYSCLK 5 3 3 External Bus Clock CLKOUT Divider The system clock divided by 1 2 4 or 8...

Page 127: ...the Nexus port NOTE The MCKO provides a nominal 50 duty cycle clock with the exception of the case that the MCKO prescaler is equal to 1 and the system clock has been divided by its prescaler There i...

Page 128: ...LPCLKDIV2 should be kept at the default setting SIU_SYSCLK LPCLKDIV2 0b00 5 4 Software Controlled Power Management 5 4 1 Module Disable MDIS Clock Gating Static clock gating is enabled by software wr...

Page 129: ...e for the eDMA and FlexRay modules Thus before setting the HLT bits for these masters software should take actions to prepare for the eDMA and FlexRay clocks to be stopped Then software sets the HLT b...

Page 130: ...4 40 MHz XTAL output The logic in the second clock domain controls the CAN interface pins The CLK_SRC bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the...

Page 131: ...required The 4 40 MHz XTAL and 16 MHz IRC can be optionally divided down by 1 2 4 8 or 16 before being supplied to the API RTC This allows the required wake up times and resolution to be met since the...

Page 132: ...uency If the system frequency source is the 16 MHz_IRC e g after wake up the IOP is clocked at 8 MHz 5 5 6 FEC Clocking The Fast Ethernet Controller is not capable of running at the target system bus...

Page 133: ...known states when the logic driving the input is powered down The RTC API block implements a real time counter and periodic interrupt The wakeup and power status block implements the logic to select p...

Page 134: ...he CRP has these major features Real time clock autonomous periodic interrupt RTC API 32 bit counter MHz XTAL RTC LOW BIU POWER FSM API CLOCKS RESET CONTROL WAKEUP POWER STATUS SEA OF GATES LOGIC 16 M...

Page 135: ...akeup logic has separate enable to support changing compare value while RTC running API interrupt with interrupt enable Operates in all modes of operation API compare value can be modified while RTC i...

Page 136: ...identified by complete name and mnemonic and lists the type of accesses allowed Table 6 1 CRP Memory Map Offset from CRP_BASE 0xFFFE_C000 Register Access Reset Value Section Page 0x0000 CRP_CLKSRC Clo...

Page 137: ...20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 TRIM128IRC 0 0 TRIM16IRC W Reset1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 These bits are only reset by power on VDD12 LVI VDD33 LVI VDDSYN LVI VDD5 Low LVI and V...

Page 138: ...us supports faster recovery time for availability of 4 40 MHz OSC after sleep recovery Supports full 4 40 MHz range of external crystals 1 4 40 MHz OSC clock active and may be used as clock source for...

Page 139: ...uests to the system if RTCF is asserted 0 RTC interrupts disabled 1 RTC interrupts enabled FRZEN Freeze Enable Bit The counter freezes on entering the debug mode as the ipg_debug is detected active on...

Page 140: ...API Compare Value The APIVAL bits are compared to an offset value based on bits 22 31 of the RTC counter If they match a wakeup interrupt request is asserted APIVAL can be updated only when APIEN 0 o...

Page 141: ...g a 1 to APIF Writing a 0 to APIF has no effect Note that the APIF bit must be cleared before entering SLEEP mode if the API is to be used as the wakeup source 0 No API interrupt 1 API interrupt ROVRF...

Page 142: ...24 25 26 27 28 29 30 31 R PWK7 PWK6 PWK5 PWK4 PWK3 PWK2 PWK1 PWK0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 7 Pin Wakeup Enable Low Register CRP_PWKENL Table 6 6 CRP_PWKENH L Field Description...

Page 143: ...13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PWKSRCIE31 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 8 Pin Wakeup Source Interrupt Enable Register...

Page 144: ...r read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R Z6VEC 0 0 0 0 0 0 0 0 0 0 Z6RST VLE W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0...

Page 145: ...ster CRP_Z0VEC Table 6 11 CRP_Z0VEC Field Descriptions Field Description Z0VEC Z0 Recovery Vector The Z0VEC value determines the initial program counter for the Z0 when exiting reset On reset the valu...

Page 146: ...ccurs for 1000 clocks 1 Reset occurs for 16 clocks Offset CRP_BASE 0x0060 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SLEEP F 0 0 0 0 0 0 0 0 0 0 0 0 RTC OVR WKF RT CWK F API WKF W...

Page 147: ...Wakeup Clock Select The WKCLKSEL bit selects the clock source used for the wakeup logic synchronizer and edge detect WKCLKSEL can be switched only when all wakeup sources are disabled 0 Clock source...

Page 148: ...he VRCSEL pin is low the 5V LVI logic is disabled and this bit has no effect LVI5HIE LVI5 High Interrupt Enable TheLVI5HIE bit enables interrupts requests to the system if LVI5HF is asserted 0 LVI5H i...

Page 149: ...us LVI5HF remains cleared LVI5NF LVIN 5V Interrupt Flag The LVI5NF bit indicates that the LVI5 LVI circuit has detected that the 5 V supply is above the defined trip limit LVI5NF is cleared by writing...

Page 150: ...urce for the RTC API during sleep but the external crystal frequency is limited to less than or equal to 8 MHz If the 4 40 MHz XTAL is powered down for sleep mode the crystal oscillator must restart o...

Page 151: ...lted the clock control block signals the CRP to enter the selected low power mode At this point the CRP has complete control of the device Figure 6 15 shows the sequence to transition from RUN mode to...

Page 152: ...P Mode Entry Diagram Run Mode Mode Transition RUN SLEEP INIT T F F F F T T T Sleep debug enabled Set Sleep Handshake bit in NPC PCR Handshake bit cleared Acknowledge clock stop ready to CCB Clock stop...

Page 153: ...le 16M IRC clkgate if not wakeup or RTC clock wait Assert system POR 1 3 clks from wakeup edge if 16 MHz_IRC enabled depends on where pin wakeup edge occurred 3 clks 16 MHz_IRC start up time if disabl...

Page 154: ...6 Bias resistor off Negate system POR Debug Enabled Block NPC debug signals dbg clk 16 MHz_IRC Assert core debug enable T F 14 15 Negate core debug enable Set dbg clk TCK TDO Pin Low Mode Transition S...

Page 155: ...ll CRP registers are reset for a POR but some like the CRP_RTCC are maintained for an external reset Note that there are no internal reset sources except POR and LVI12 active in sleep There are four m...

Page 156: ...is enabled by setting the NPC PCR LP_DBG_EN bit prior to entry into sleep modes On entry into sleep mode if the NPC PCR LP_DBG_EN bit is set the CRP sets the NPC PCR SLEEP_SYNC bit to inform the debu...

Page 157: ...es A block diagram of the SOC blocks and the connections between them to support debug on sleep wakeup is given in Figure 6 19 NOTE The CRP enables only the debug pins that were enabled prior to sleep...

Page 158: ...ed by software and by POR Autonomous periodic interrupt support includes 10 bit compare value to support wake up intervals of 1 0 ms to 1 s Wake up logic has separate enable to support changing compar...

Page 159: ..._RTCC ROVREN bit An RTC counter rollover with this bit and the CRP_PSCR RTCOVRWKEN bit set causes a wakeup from sleep mode The rollover wakeup flag is captured in the CRP_PSCR WKRLLOVRF bit An interru...

Page 160: ...C status and control register Section 6 2 2 2 RTC Control Register CRP_RTCC RTC counter register Section 6 2 2 4 RTC Counter Register CRP_RTCCNT 0 1 2 CLKSEL 3 128 kHz IRC 16 MHz IRC 32 kHz_XTAL CNTEN...

Page 161: ...The LVI33SYN monitors VDDSYN and triggers a reset when it falls below the assert level LVI5_VDDA 3 3 V 5 V supply The LVI_VDDA monitors VDDA and triggers an interrupt or internal reset when it drops d...

Page 162: ...Clocks Reset and Power CRP PXN20 Microcontroller Reference Manual Rev 1 6 30 Freescale Semiconductor...

Page 163: ...agram of the FMPLL illustrates the functionality and interdependence of major blocks see Figure 7 1 Shaded blocks represent analog circuit components that make up the core analog portion of the FMPLL...

Page 164: ...e two main modes of FMPLL PLL Off mode and normal mode These modes are briefly described in this section When PLL Off mode is selected the FMPLL is turned off and the end system user must select a dif...

Page 165: ...0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 LOLF LOC MODE PLL SEL PLL REF LOCKS LOCK LOCF CAL DONE CAL PASS W w1c w1...

Page 166: ...L Lock Status Bit The LOCKS bit is a sticky indication of PLL lock status LOCKS is set by the lock detect circuitry when the PLL acquires lock after 1 a system reset or 2 a write to the ESYNCR2 which...

Page 167: ...3 CALDONE Calibration Complete The CALDONE bit is an indication of whether the calibration sequence has been completed since the last time modulation was enabled If CALDONE 0 then the calibration sequ...

Page 168: ...in Table 7 4 causes the PLL to produce an unpredictable output clock The output frequency of the divider must equal fpllref see the PXN20 Microcontroller Data Sheet When the EPREDIV bits are changed t...

Page 169: ...e FMPLL The bit fields in the ESYNCR2 behave as described in Figure 7 4 Table 7 5 Pre divider Ratios EPREDIV Input Divide Ratio EPREDIV 1 0000 1 default for PXN20 0001 2 0010 3 0011 4 0100 5 0101 6 01...

Page 170: ...ted The LOLRE bit has no effect in PLL Off mode 0 Assert reset on loss of lock is disabled 1 Assert reset on loss of lock LOCRE Loss of Clock Reset Enable The LOCRE bit determines how the integration...

Page 171: ...en numbered ERFD settings which would result in odd divide ratios are not allowed The decimal equivalent of the ERFD binary number is substituted into the equation from Table 7 11 Note The ERFD divide...

Page 172: ...log loop For the remainder of this chapter the term reference frequency and the symbol Fref indicate the output of the pre divider circuit This is the clock on which frequency multiplication is perfor...

Page 173: ...he frequency relationship but is not guaranteed The PLL lock status is reflected in the LOCK status bit in the SYNSR A sticky lock status indication LOCKS is also provided The lock detect function use...

Page 174: ...to the phase frequency detector PFD see Figure 7 1 When the reference or feedback clock frequency falls below a minimum frequency the LOC circuitry considers the clock to have failed and a loss of clo...

Page 175: ...the FMPLL can be divided down in powers ranging from 2 to 128 to reduce the system frequency with the ERFD The ERFD is not contained in the feedback loop of the PLL so changing the ERFD bits does not...

Page 176: ...uency is 48 times the reference frequency The presence of the MFD in the loop allows the PLL to perform frequency multiplication or synthesis 7 4 3 3 5 Programming System Clock Frequency In normal PLL...

Page 177: ...equency modulation is desired leave ERFD programmed to ERFD 1 until after completing the steps in Section 7 4 3 4 2 Programming System Clock Frequency With Frequency Modulation 6 If frequency modulati...

Page 178: ...ror incurred is not corrected The calibration system reuses the two counters in the lock detect circuit the reference and feedback counters The reference counter remains clocked by the reference clock...

Page 179: ...System Clock Frequency With Frequency Modulation The following steps illustrate proper programming of the frequency modulation mode These steps ensure proper operation of the calibration routine and p...

Page 180: ...alid reference clock is detected by the internal clock monitor circuit Internal to the PLL the VCO is held in reset until the negation of the POR signal This prevents the PLL from attempting to lock b...

Page 181: ...curred In PLL Off mode the PLL cannot lock therefore a loss of lock condition cannot occur and LOLRE has no effect 7 5 3 PLL Loss of Clock Reset When a loss of clock condition is recognized RESET is a...

Page 182: ...Frequency Modulated Phase Locked Loop FMPLL PXN20 Microcontroller Reference Manual Rev 1 7 20 Freescale Semiconductor...

Page 183: ...s the external pin boot configuration logic The pad configuration block controls the static electrical characteristics of I O pins The GPIO block provides uniform and discrete input output control of...

Page 184: ...ation MCU reset configuration via external pins Pad configuration control System reset monitoring and generation Reset RESET Configuration SIU Registers Reset Controller Pad Interface Pad Ring Pad Con...

Page 185: ...lection of ADC trigger inputs Allows selection of interrupt requests among external pins Allows selection of eMIOS inputs between external pins and deserialized DSPI outputs Allows selection of eMIOS...

Page 186: ...2 27 Parallel GPIO Pin Data Output Register 0 SIU_PGPDO0 through Section 8 3 2 36 Parallel GPIO Pin Data Input Register 4 SIU_PGPDI4 Section 8 3 2 37 Masked Parallel GPIO Pin Data Output Register 1 SI...

Page 187: ...4 ADC trigger input select register 4 R W 0x0000_0000 8 3 2 18 8 35 0x0914 0x097F Reserved 0x0980 SIU_CCR Chip configuration register R W 0x000U_0000 8 3 2 19 8 36 0x0984 SIU_ECCR External clock contr...

Page 188: ...000_0000 8 3 2 37 8 52 0x0C88 SIU_MPGPDO2 Masked parallel GPIO data output register 2 W 0x0000_0000 8 3 2 38 8 53 0x0C8C SIU_MPGPDO3 Masked parallel GPIO data output register 3 W 0x0000_0000 8 3 2 39...

Page 189: ...0x0D4C 0x0D53 Reserved 0x0D54 SIU_EMIOSB eMIOS select register for DSPI_B R W 0x0000_0000 8 3 2 56 8 64 0x0D58 SIU_DSPIBHLB SIU_DSPIBH L select register for DSPI_B R W 0x0000_0000 8 3 2 57 8 64 0x0D5...

Page 190: ...PA11 11 FFFE_8056 FFFE_880B PA12 12 FFFE_8058 FFFE_880C PA13 13 FFFE_805A FFFE_880D PA14 14 FFFE_805C FFFE_880E PA15 15 FFFE_805E FFFE_880F PB0 16 FFFE_8060 FFFE_8610 FFFE_8810 PB1 17 FFFE_8062 FFFE_8...

Page 191: ...E_882D PC14 46 FFFE_809C FFFE_862E FFFE_882E PC15 47 FFFE_809E FFFE_862F FFFE_882F PD0 48 FFFE_80A0 FFFE_8630 FFFE_8830 PD1 49 FFFE_80A2 FFFE_8631 FFFE_8831 PD2 50 FFFE_80A4 FFFE_8632 FFFE_8832 PD3 51...

Page 192: ...FE_884D PE14 78 FFFE_80DC FFFE_864E FFFE_884E PE15 79 FFFE_80DE FFFE_864F FFFE_884F PF0 80 FFFE_80E0 FFFE_8650 FFFE_8850 PF1 81 FFFE_80E2 FFFE_8651 FFFE_8851 PF2 82 FFFE_80E4 FFFE_8652 FFFE_8852 PF3 8...

Page 193: ...86D PG14 110 FFFE_811C FFFE_866E FFFE_886E PG15 111 FFFE_811E FFFE_866F FFFE_886F PH0 112 FFFE_8120 FFFE_8670 FFFE_8870 PH1 113 FFFE_8122 FFFE_8671 FFFE_8871 PH2 114 FFFE_8124 FFFE_8672 FFFE_8872 PH3...

Page 194: ...8156 FFFE_868B FFFE_888B PJ12 140 FFFE_8158 FFFE_868C FFFE_888C PJ13 141 FFFE_815A FFFE_868D FFFE_888D PJ14 142 FFFE_815C FFFE_868E FFFE_888E PJ15 143 FFFE_815E FFFE_868F FFFE_888F PK0 144 FFFE_8160 F...

Page 195: ...the device package type as defined in Table 8 3 MASKNUM_MAJOR default value is 0x0 for the device s initial mask set and changes for each major mask set revision MASKNUM_MINOR default value is 0x0 for...

Page 196: ...us bits for all of the requesting resets are set Simultaneous reset requests are prioritized When reset requests of different priorities occur on the same clock cycle the lower priority reset request...

Page 197: ...was not a loss of clock reset 1 Last reset source the reset controller acknowledged was a loss of clock reset WDRS Watchdog Timer Reset Status 0 Last reset source the reset controller acknowledged wa...

Page 198: ...heckstop Reset Enable enable secondary CPU Z0 checkstop to generate reset Writing a 1 to this bit enables a reset when the e200z0 checkstop reset request input is asserted The checkstop reset request...

Page 199: ...6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EIF 15 EIF 14 EIF 13 EIF 12 EIF 11 EIF 10 EIF 9 EIF 8 EIF 7 EIF 6 EIF 5 EIF 4 EIF 3 EIF 2 EIF 1 EIF 0 W Reset w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w...

Page 200: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 6 SIU DMA Interrupt Request Enable Register SIU_DIRER Table 8 8 SIU_DIRER Field Descriptions Field Description EIREn External Interrupt Request Enable n En...

Page 201: ...0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVF 15 OVF 14 OVF 13 OVF 12 OVF 11 OVF 10 OVF 9 OVF 8 OVF 7 OVF 6 OVF 5 OVF 4 OVF 3 OVF 2 OVF 1 OVF 0 W Reset w1c w1c w1c w1c w1c w1c...

Page 202: ...abled 1 Overrun request enabled Offset SIU_BASE 0x0028 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NREE01 NREE11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 203: ...FEE 1 IFEE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Once written the NFEEn bits cannot be changed until the next reset Figure 8 11 IRQ Falling Edge Event Enable Register SIU_IFEER Table 8 13 SIU_IF...

Page 204: ...nts for synchronization of the IRQ input pins with the system clock Offset SIU_BASE 0x0034 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FNMI0 FNMI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset...

Page 205: ...registers are undefined when the corresponding IBE bit is negated The SIU_PCRs are 16 bit registers that may be read or written as 32 bit values aligned on 32 bit address boundaries Table 8 16 describ...

Page 206: ...he output signals are driven to the value of this field The actual drive strengths are defined by the implementation of the pad devices for a given device Note DSC is applicable to fast pads only See...

Page 207: ...output signals are driven according to the value of this field Actual slew rate is dependent on the pad type and load See the PXN20 Microcontroller Data Sheet for this information Note SRC is applica...

Page 208: ...rpose inputs Therefore there are no output data registers associated with these pins The SIU_GPDOn registers are written to by software to drive data out on the external GPIO pin Each byte of a regist...

Page 209: ...e register If the register is read it returns the value written 0 VOL driven on the external GPIO pin when the pin is configured as an output 1 VOH driven on the external GPIO pin when the pin is conf...

Page 210: ...SIU_GPDIn register reflects the actual state of the output pin 112_115 116_119 120_123 124_127 0x0670 0x0674 0x0678 0x067C PH0 PH3 PH4 PH7 PH8 PH11 PH12 PH15 128_131 132_135 136_139 140_143 0x0680 0x0...

Page 211: ...8 0x081C PB0 PB3 PB4 PB7 PB8 PB11 PB12 PB15 32_35 36_39 40_43 44_47 0x0820 0x0824 0x0828 0x082C PC0 PC3 PC4 PC7 PC8 PC11 PC12 PC15 48_51 52_55 56_59 60_63 0x0830 0x0834 0x0838 0x083C PD0 PD3 PD4 PD7 P...

Page 212: ...L1 Field Descriptions Field Description1 ESEL15 External IRQ Input Select 15 Specifies input for IRQ15 00 PB15 pin 01 PC15 pin 10 PD15 pin 11 ISEL2 ESEL14 External IRQ Input Select 14 Specifies input...

Page 213: ...D7 pin 11 ISEL2 ESEL6 External IRQ Input Select 6 Specifies input for IRQ6 00 PB6 pin 01 PC6 pin 10 PD6 pin 11 ISEL2 ESEL5 External IRQ Input Select 5 Specifies input for IRQ5 00 PB5 pin 01 PC5 pin 10...

Page 214: ...ecifies input for IRQ1 00 PB1 pin 01 PC1 pin 10 PD1 pin 11 ISEL2 ESEL0 External IRQ Input Select 0 Specifies input for IRQ0 00 PB0 pin 01 PC0 pin 10 PD0 pin 11 ISEL2 1 Pins specified in this table mus...

Page 215: ...SEL1 ESEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 20 IMUX Select Register 2 SIU_ISEL2 Table 8 22 SIU_ISEL2 Field Descriptions Field Description ESEL15 External IRQ Input Select 15 Specifies...

Page 216: ...pin 11 ISEL2A ESEL6 External IRQ Input Select 6 Specifies input for IRQ6 00 PE6 pin 01 PF6 pin 10 PG6 pin 11 ISEL2A ESEL5 External IRQ Input Select 5 Specifies input for IRQ5 00 PE5 pin 01 PF5 pin 10...

Page 217: ...9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 TSEL1 0 TSEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 2...

Page 218: ...input signal to the SIU The match input is asserted if the serial boot password provided by the user matches the password stored in the flash 0 Match input signal is negated 1 Match input signal is as...

Page 219: ...but reads return the written value Figure 8 23 External Clock Control Register SIU_ECCR Table 8 25 SIU_ECCR Field Descriptions Field Description ECEN External Clock Enable The ECEN bit enables CLKOUT...

Page 220: ...see Section 5 3 5 Peripheral Clock Dividers Offset SIU_BASE 0x0988 SIU_GPR0 0x098C SIU_GPR1 0x0990 SIU_GPR2 0x0994 SIU_GPR3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R GP W Reset 0...

Page 221: ...tem clock supplied by 16 MHz IRC 01 System clock supplied by 4 40 MHz_XTAL 10 System clock supplied by FMPLL 11 Reserved defaults to 16 MHz IRC Note The default SYSCLKSEL value may be modified by the...

Page 222: ...his bit halts the FLEXCAN_F module HLT11 Halt bit 11 Setting this bit halts the FLEXCAN_E module HLT12 Halt bit 12 Setting this bit halts the FLEXCAN_D module HLT13 Halt bit 13 Setting this bit halts...

Page 223: ...26 HLT 27 HLT 28 HLT 29 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reserved do not write to this bit 2 Writes to this bit are reflected in the SIU_HLT1 and SIU_HLTACK1 register but have no other ef...

Page 224: ...CK11 Halt acknowledge bit 11 When this bit is set the FLEXCAN_E module is halted HLTACK12 Halt acknowledge bit 12 When this bit is set the FLEXCAN_D module is halted HLTACK13 Halt acknowledge bit 13 W...

Page 225: ...re is halted Note This flag indicates a core generated halt not a halt caused by writing to SIU_HLT10 HLT0 HLTACK1 Halt acknowledge bit 1 When this bit is set the Z0 core is halted Note This flag indi...

Page 226: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EMIOSSEL27 EMIOSSEL26 EMIOSSEL25 EMIOSSEL24 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 30 eMIOS Select Register 0 SIU_EMIOS_SEL0 Offset SIU_BASE 0x09...

Page 227: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 33 eMIOS Select Register 3 SIU_EMIOS_SEL3 Table 8 31 SIU_EMIOS_SELn Field Descriptions Field Description EMIOSSELn eMIOS Channel n connection options 0000 0011 e...

Page 228: ...10 Reserved 11 Reserved ESEL12 External IRQ Input Select 12 Specifies input for IRQ12 00 PH12 pin 01 PJ12 pin 10 Reserved 11 Reserved ESEL11 External IRQ Input Select 11 Specifies input for IRQ11 00...

Page 229: ...fies input for IRQ4 00 PH4 pin 01 PJ4 pin 10 PK4 pin 11 Reserved ESEL3 External IRQ Input Select 3 Specifies input for IRQ3 00 PH3 pin 01 PJ3 pin 10 PK3 pin 11 Reserved ESEL2 External IRQ Input Select...

Page 230: ...output for PC 0 15 and PD 0 15 Reads and writes to this register are coherent with the registers SIU_GPDO32_35 SIU_GPDO36_39 SIU_GPDO40_43 SIU_GPDO44_47 SIU_GPDO48_51 SIU_GPDO52_55 SIU_GPDO56_59 and...

Page 231: ...0_123 and SIU_GPDO124_127 8 3 2 31 Parallel GPIO Pin Data Output Register 4 SIU_PGPDO4 The SIU_PGPDO4 register contains the parallel GPIO pin data output for PJ 0 15 and PK 0 10 Reads and writes to th...

Page 232: ...PD15 Writes have no effect Reads of this register are coherent with the registers SIU_GPDI32_35 SIU_GPDI36_39 SIU_GPDI40_43 SIU_GPDI44_47 SIU_GPDI48_51 SIU_GPDI52_55 SIU_GPDI56_59 and SIU_GPDI60_63 O...

Page 233: ...H0 PH15 Writes have no effect Reads of this register are coherent with the registers SIU_GPDI96_99 SIU_GPDI100_103 SIU_GPDI104_107 SIU_GPDI108_111 SIU_GPDI112_115 SIU_GPDI116_119 SIU_GPDI120_123 and S...

Page 234: ...in the data register for which the corresponding mask bit is set For example if the current state of the port B parallel GPIO pin data output register is 0x1234 and you want to change only bits 12 15...

Page 235: ...o this register are coherent with the registers SIU_GPDO48_51 SIU_GPDO52_55 SIU_GPDO56_59 and SIU_GPDO60_63 Offset SIU_BASE 0x0C84 Access User write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0...

Page 236: ...SIU_GPDO84_87 SIU_GPDO88_91 and SIU_GPDO92_95 Offset SIU_BASE 0x0C8C Access User write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PD_MASK 0 15 Reset 0 0 0 0 0 0 0 0...

Page 237: ...SIU_GPDO116_119 SIU_GPDO120_123 and SIU_GPDO124_127 Offset SIU_BASE 0x0C94 Access User write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PF_MASK 0 15 Reset 0 0 0 0...

Page 238: ...PDO144_147 SIU_GPDO148_151 and SIU_GPDO152_154 Offset SIU_BASE 0xC9C Access User write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PH_MASK 0 15 Reset 0 0 0 0 0 0 0 0...

Page 239: ...BASE 0x0D00 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MASK 31 MASK 30 MASK 29 MASK 28 MASK 27 MASK 26 MASK 25 MASK 24 MASK 23 MASK 22 MASK 21 MASK 20 MASK 19 MASK 18 MASK 17 MASK...

Page 240: ...s in the output register for which the corresponding mask bit is set Offset SIU_BASE 0x0D04 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MASK 15 MASK 14 MASK 13 MASK 12 MASK 11 MASK...

Page 241: ...0 0 0 0 0 0 0 0 0 Figure 8 56 Masked Serial GPO Register for DSPI_B High SIU_DSPIBH Table 8 35 SIU_DSPIBH Field Descriptions Field Description MASKn Mask Bit This bit controls the write access to the...

Page 242: ...his register 0 Logic low value is driven for the corresponding GPO for DSPI_B when this output is selected in the DSPI serialization module 1 Logic high value is driven for the corresponding GPO for D...

Page 243: ...1 DATA 10 DATA 9 DATA 8 DATA 7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 59 Masked Serial GPO Register for DSPI_C Low SIU_DSPICL Table 8 38 SIU_...

Page 244: ...rresponding GPO for DSPI_D when this output is selected in the DSPI serialization module 1 Logic high value is driven for the corresponding GPO for DSPI_D when this output is selected in the DSPI seri...

Page 245: ...EMIOSA Table 8 41 SIU_EMIOSA Field Descriptions Field Description EMIOSn eMIOS Channel Enable 0 This eMIOS channel is not enabled 1 This eMIOS channel is enabled Offset SIU_BASE 0x0D48 Access User rea...

Page 246: ...4 EMIOS 13 EMIOS 12 EMIOS 11 EMIOS 10 EMIOS 9 EMIOS 8 EMIOS 7 EMIOS 6 EMIOS 5 EMIOS 4 EMIOS 3 EMIOS 2 EMIOS 1 EMIOS 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 64 eMIOS Select Register for DSPI...

Page 247: ...B High DSPIBLn Data Path Enable for DSPI_B Low 0 Data path disabled to DSPI_B Low 1 Data path enabled to DSPI_B Low Offset SIU_BASE 0x0D64 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 248: ...lect Register for DSPI_C SIU_DSPICHLC Table 8 46 SIU_DSPICHLC Field Descriptions Field Description DSPICHn Data Path Enable for DSPI_C High 0 Data path disabled to DSPI_C High 1 Data path enabled to D...

Page 249: ...22 DSPI DH 21 DSPI DH 20 DSPI DH 19 DSPI DH 18 DSPI DH 17 DSPI DH 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DSPI DL 15 DSPI DL 14 DSPI DL 13 DSPI DL...

Page 250: ...ion details 8 4 3 External Interrupt There are 16 external interrupt inputs IRQ0 IRQ15 to the SIU The IRQn inputs can be configured for rising or falling edge events or both Each IRQn input has a corr...

Page 251: ...that can be used to access as many as 32 GPIO bits in single and word sized accesses The values read written to these parallel register is coherent with the data read written to the SIU_GPDOn and SIU...

Page 252: ...ing The 16 SIU external interrupt inputs can be connected to one of nine external pins The input source for each SIU external interrupt is individually specified in the IMUX Select Register 1 SIU_ISEL...

Page 253: ...IOS DSPI Multiplexing The Serialization Data Register from each of the four DSPI modules can be connected to the EMIOS channel outputs if selected by the SIU_EMIOSx registers or the Masked Serial GPO...

Page 254: ...nnel output SIU_DSPIAHLA SIU_DSPIA DSPIA DSPI Serialization Data Register SIU_EMIOSD SIU_EMIOSC SIU_EMIOSB EMIOS channel output EMIOS channel output EMIOS channel output SIU_DSPIAHLB SIU_DSPIAHLD SIU_...

Page 255: ...l MCU resources and external memory address space Location and detection of user boot code in the internal flash Automatic switch to serial boot mode if internal flash is blank or invalid Supports use...

Page 256: ...used for all code and all boot configuration data After the BAM has completed the boot process user code may enable the external bus interface if required 9 1 2 4 Serial Boot Mode This mode of operati...

Page 257: ...n If the CRP_Z6VEC register value is 0xFFFF_FFFC the BAM code is executed after the negation of reset and before user code starts To prevent the execution of the BAM code when exiting sleep mode chang...

Page 258: ...of the DISNEX bit to determine if the serial password downloaded in serial boot mode is compared to a fixed public value 0xFEED_FACE_CAFE_BEEF or is compared to a flash value stored in the shadow row...

Page 259: ...hysical Base Address Size Attributes 0 Peripheral bridge and BAM 0xFFF0_0000 0xFFF0_0000 1 MB Cache inhibited Guarded Big Endian Global PID 1 Internal flash 0x0000_0000 0x0000_0000 256 MB Cache enable...

Page 260: ...CHW is a 16 bit value that contains a fixed 8 bit boot identifier and some configuration bits The RCHW is expected to be the first halfword in one of the low address space small flash blocks The memor...

Page 261: ...cription WTE Watchdog timer enable This bit determines if the software watchdog timer is disabled 0 Disable software watchdog timer 1 Software watchdog timer maintains its default state out of reset i...

Page 262: ...ains configured as GPIO input until a valid eSCI byte is received before a valid CAN message The FlexCAN controller is configured to operate at a baud rate system clock frequency 40 using the standard...

Page 263: ...IRC The BAM program ignores eSCI errors All received data is assumed to be good and is echoed out on the TXD_A signal Upon reception of a valid CAN message with ID 0x011 that contains 8 bytes of data...

Page 264: ...tures are sent most significant byte MSB first When the CAN is used for serial download the data is packed into standard CAN messages in the following manner A message with 0x0011 ID and 8 byte length...

Page 265: ...rotocol 2 Download start address size of download and VLE bit The next 8 bytes received by the MCU are considered to contain a 32 bit start address the VLE mode bit and a 31 bit code length see Figure...

Page 266: ...otocol NOTE The code that is downloaded and executed must periodically refresh the platform watchdog timer or change the timeout period to a value that will not cause resets during normal operation Th...

Page 267: ...the SRAM will be written with zero value due to incomplete memory decoding So when using the serial download feature of the BAM make sure that the maximum address of the downloaded code does not exce...

Page 268: ...Boot Assist Module BAM PXN20 Microcontroller Reference Manual Rev 1 9 14 Freescale Semiconductor...

Page 269: ...ny interrupt source to generate an interrupt request to either the Z6 or Z0 or to both the Z6 and Z0 cores When multiple tasks share a resource coherent accesses to that resource need to be supported...

Page 270: ...errupt Acknowledge Register Processor 1 End of Interrupt Register Processor 0 End of Interrupt Register 1 Processor 1 Interrupt Vector 9 316 Interrupt Vector 9 Request Selector Priority Arbitrator Hig...

Page 271: ...to or from a LIFO Ability to modify the ISR or task priority modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources Low latency three clocks from...

Page 272: ...interrupt vector offset register IVOR4 NOTE Since bits IVOR4 28 31 are not part of the offset value for the Z6 the vector offset must be located on a quad word 16 byte aligned location in memory For t...

Page 273: ...se INTVEC does not update to the higher priority request until the lower priority interrupt request is acknowledged by reading the INTC_IACKR_PRCn The reading also pushes the PRI value in the INTC cur...

Page 274: ...onfigurable Typical program flow for hardware vector mode is shown in Figure 10 6 Figure 10 6 Program Flow Hardware Vector Mode In hardware vector mode the interrupt exception handler address is speci...

Page 275: ...priority 10 2 External Signal Description The INTC has no direct external MCU signals However there are external pins that can be configured in the SIU as external interrupt request input pins When co...

Page 276: ...10 12 0x0010 INTC_IACKR_PRC0 INTC interrupt acknowledge register for processor 0 Z6 R1 W 1 When the HVEN bit in the INTC module configuration register INTC_MCR is asserted a read of the INTC_IACKR_PR...

Page 277: ...INTC_EOIR_PRC1 does not affect the operation of the write 10 3 2 1 INTC Module Configuration Register INTC_MCR The module configuration register is used to configure options of the INTC Offset INTC_BA...

Page 278: ...are mode only the Vector Table Entry Size for Processor 0 Z6 The VTES_PRC0 bit controls the number of 0s to the right of INTVEC_PRC0 in INTC_IACKR_PRC0 If the contents of INTC_IACKR_PRC0 are used as a...

Page 279: ...between the accesses An mbar or msync instruction is also necessary after accessing the resource but before lowering the PRI field Refer to Section 10 5 5 2 Ensuring Coherency for example code to ensu...

Page 280: ...or 1 Z0 INTC_CPR_PRC1 Table 10 5 INTC_CPR_PRC1 Field Descriptions Field Description PRI Priority The function of this register is the same as described for processor 0 Z6 in Section 10 3 2 2 INTC Curr...

Page 281: ...tibility the TLB entry covering the INTC_IACKR_PRCn must be configured to be guarded In software vector mode the INTC_IACKR_PRCn must be read before setting MSR EE No synchronization instruction is ne...

Page 282: ...st significant bits INTVEC_PRC11 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 When the VTES_PRC1 bit in INTC_MCR is asserted INTVEC_PRC1 is shifted to the left one bit Bit 29 is read as 0 VTBA_PRC1 i...

Page 283: ...0 0 0 0 Figure 10 15 INTC End of Interrupt Register for Processor 1 Z0 INTC_EOIR_PRC1 Offset INTC_BASE_ADDR 0x0020 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 CLR0 0 0...

Page 284: ...d Descriptions Field Description SET Set Flag Bits Writing a 1 sets the corresponding CLRn bit Writing a 0 has no effect Each SETn is always read as a 0 CLR Clear Flag Bits CLRn is the flag bit Writin...

Page 285: ...x0050 INTC_PSR176_179 0x00F0 INTC_PSR20_23 0x0054 INTC_PSR180_183 0x00F4 INTC_PSR24_27 0x0058 INTC_PSR184_187 0x00F8 INTC_PSR28_31 0x005C INTC_PSR188_191 0x00FC INTC_PSR32_35 0x0060 INTC_PSR192_195 0x...

Page 286: ...PRIn field of an INTC_PSRn_n must not be modified while the corresponding peripheral or software settable interrupt request is asserted INTC_PSR108_111 0x00AC INTC_PSR268_271 0x014C INTC_PSR112_115 0x...

Page 287: ...in size This difference in size combined with the different starting offset for the e200z0 interrupt requests makes it impossible for the two cores to share a single interrupt table To solve this eith...

Page 288: ...0 eDMA 1 13 0x00D0 0x0834 eDMA 2 14 0x00E0 0x0838 eDMA 3 15 0x00F0 0x083C eDMA 4 16 0x0100 0x0840 eDMA 5 17 0x0110 0x0844 eDMA 6 18 0x0120 0x0848 eDMA 7 19 0x0130 0x084C eDMA 8 20 0x0140 0x0850 eDMA 9...

Page 289: ...0x0210 0x0884 eDMA 22 34 0x0220 0x0888 eDMA 23 35 0x0230 0x088C eDMA 24 36 0x0240 0x0890 eDMA 25 37 0x0250 0x0894 eDMA 26 38 0x0260 0x0898 eDMA 27 39 0x0270 0x089C eDMA 28 40 0x0280 0x08A0 eDMA 29 41...

Page 290: ...57 0x0390 0x08E4 SIU External Interrupts 15 4 58 0x03A0 0x08E8 EMIOS 0 EMIOS channels 0 to 23 see Interrupt vectors 262 269 59 0x03B0 0x08EC EMIOS 1 60 0x03C0 0x08F0 EMIOS 2 61 0x03D0 0x08F4 EMIOS 3...

Page 291: ...0 0x0958 Reserved ADC_B 87 0x0570 0x095C Reserved ADC_B 88 0x0580 0x0960 Reserved ADC_C 89 0x0590 0x0964 Reserved ADC_C 90 0x05A0 0x0968 Reserved ADC_C 91 0x05B0 0x096C Reserved Reserved 92 0x05C0 0x0...

Page 292: ...0x0710 0x09C4 SCI_A SCI_A to SCI_D see Interrupt vectors 270 273 114 0x0720 0x09C8 SCI_B 115 0x0730 0x09CC SCI_C 116 0x0740 0x09D0 SCI_D 117 0x0750 0x09D4 DSPI_A FIFO Overflow Underflow DSPI_A see In...

Page 293: ...CAN_A Buffer 7 138 0x08A0 0x0A28 FLEXCAN_A Buffer 8 139 0x08B0 0x0A2C FLEXCAN_A Buffer 9 140 0x08C0 0x0A30 FLEXCAN_A Buffer 10 141 0x08D0 0x0A34 FLEXCAN_A Buffer 11 142 0x08E0 0x0A38 FLEXCAN_A Buffer...

Page 294: ...0x0A40 0x0A90 FLEXCAN_B Buffer 4 165 0x0A50 0x0A94 FLEXCAN_B Buffer 5 166 0x0A60 0x0A98 FLEXCAN_B Buffer 6 167 0x0A70 0x0A9C FLEXCAN_B Buffer 7 168 0x0A80 0x0AA0 FLEXCAN_B Buffer 8 169 0x0A90 0x0AA4 F...

Page 295: ...186 0x0BA0 0x0AE8 FLEXCAN_C Buffer 5 187 0x0BB0 0x0AEC FLEXCAN_C Buffer 6 188 0x0BC0 0x0AF0 FLEXCAN_C Buffer 7 189 0x0BD0 0x0AF4 FLEXCAN_C Buffer 8 190 0x0BE0 0x0AF8 FLEXCAN_C Buffer 9 191 0x0BF0 0x0...

Page 296: ...LEXCAN_D Buffer 5 208 0x0D00 0x0B40 FLEXCAN_D Buffer 6 FlexCAN_D continued 209 0x0D10 0x0B44 FLEXCAN_D Buffer 7 210 0x0D20 0x0B48 FLEXCAN_D Buffer 8 211 0x0D30 0x0B4C FLEXCAN_D Buffer 9 212 0x0D40 0x0...

Page 297: ...LEXCAN_E Buffer 5 229 0x0E50 0x0B94 FLEXCAN_E Buffer 6 230 0x0E60 0x0B98 FLEXCAN_E Buffer 7 231 0x0E70 0x0B9C FLEXCAN_E Buffer 8 232 0x0E80 0x0BA0 FLEXCAN_E Buffer 9 233 0x0E90 0x0BA4 FLEXCAN_E Buffer...

Page 298: ...0 0x0BE4 FLEXCAN_F Buffer 5 250 0x0FA0 0x0BE8 FLEXCAN_F Buffer 6 251 0x0FB0 0x0BEC FLEXCAN_F Buffer 7 252 0x0FC0 0x0BF0 FLEXCAN_F Buffer 8 253 0x0FD0 0x0BF4 FLEXCAN_F Buffer 9 254 0x0FE0 0x0BF8 FLEXCA...

Page 299: ...ee Interrupt vectors 117 126 275 0x1130 0x0C4C DSPI_C End Of Queue 276 0x1140 0x0C50 DSPI_C Tx FIFO Fill Request 277 0x1150 0x0C54 DSPI_C Transfer complete 278 0x1160 0x0C58 DSPI_C Rx FIFO Drain Reque...

Page 300: ...0x0CB4 Reserved Reserved for On Platform 302 0x12E0 0x0CB8 Reserved 303 0x12F0 0x0CBC Reserved 304 0x1300 0x0CC0 Reserved 305 0x1310 0x0CC4 Reserved 306 0x1320 0x0CC8 SCI_J SCI_J to SCI_M see Interrup...

Page 301: ...uest to the INTC to the time that the INTC starts to drive the interrupt request to the processor is three clocks Interrupt requests from devices external to the PXN20 are classified as peripheral int...

Page 302: ...s higher than the current priority for a given processor then the interrupt request to the processor is asserted Also a unique vector for the preempting peripheral or software settable interrupt reque...

Page 303: ...t LIFO The LIFO stores the preempted PRI values from the associated INTC_CPR_PRC0 or INTC_CPR_PRC1 Therefore because these priorities are stacked within the INTC if interrupts need to be enabled durin...

Page 304: ...rrupt Exception Handler Before the interrupt exception handling completes INTC end of interrupt register INTC_EOIR_PRC0 or INTC_EOIR_PRC1 must be written When written the associated LIFO is popped so...

Page 305: ...preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the interrupt requ...

Page 306: ...equence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initialization configure VTES_PRC0 VTES_PRC1 HVEN_PRC0...

Page 307: ...re store to clear flag bit has completed lis r3 INTC_EOIR_PRCn ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR_PRCn wrteei 0 disable processor recognition of in...

Page 308: ...of the tasks under its control typically execute with PRI in INTC current priority register INTC_CPR_PRC0 or INTC_CPR_PRC1 having a value of 0 The RTOS executes the tasks according to whatever priori...

Page 309: ...0 13 Order of ISR Execution Example Step Step Description Code Executing at End of Step PRI in INTC_CPR at End of Step RTOS ISR1081 1 ISR108 executes for peripheral interrupt request 100 because the f...

Page 310: ...iority higher than 3 can preempt ISR1 10 5 5 2 Ensuring Coherency Non coherent accesses to a shared resource can occur As an example ISR1 and ISR2 both share a resource ISR1 has a lower priority there...

Page 311: ...for that peripheral interrupt request C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent data block D PRI in INTC_CPR now at 3 reflecting the write This write just be...

Page 312: ...it also allows easier management of ISRs with similar deadlines that share a resource They do not need to use the PCP to access the shared resource 10 5 7 Software Settable Interrupt Requests The soft...

Page 313: ...IRn is asserted before again writing a 1 to the SETn bit Another application is the sharing of a block of data For example a first processor has completed accessing a block of data and wants a second...

Page 314: ...d properly Their PRIn values in INTC priority select registers INTC_PSR0 INTC_PSR315 must be selected to be at or lower than the priority of the ISR that cleared their flag bits Otherwise those flag b...

Page 315: ...igured to use the PC6 and PC5 pins as non maskable interrupts NMI by providing a path to the critical interrupt input of the e200z6 and e200z0 cores respectively After the SIU is configured by user co...

Page 316: ...200z0 processor s Machine Check Register MCR ee ce and the Hardware Implementation register HID1 are sent to the ECSM to determine when interrupt servicing is enabled and when high priority elevation...

Page 317: ...st of the masters in the system For more information see Chapter 19 Error Correction Status Module ECSM 10 7 3 eDMA Dynamic Interrupt Priority Elevation The eDMA can handle dynamic priority elevation...

Page 318: ...Interrupts and Interrupt Controller INTC PXN20 Microcontroller Reference Manual Rev 1 10 50 Freescale Semiconductor...

Page 319: ...PXN20 provides 592 KB of SRAM The PXN21 provides 128 KB of SRAM 11 1 1 Block Diagram Figure 11 1 Crossbar Arrangement Showing Embedded Memories PXN20 AHB Crossbar Switch PFlash Controller 4 x 128 Page...

Page 320: ...ata integrity Supports byte 8 bit half word 16 bit word 32 bit and long word 64 bit writes for optimal use of memory User transparent ECC encoding and decoding for byte half word and word accesses Sep...

Page 321: ...tion The RAM is implemented in two blocks to allow the many masters on the device to access this memory without significantly blocking between the masters This is necessary since some masters such as...

Page 322: ...rrors detecting and either correcting or flagging errors 2 The write data bytes 1 2 or 4 byte segment are merged with the corrected 64 bits on the data bus 3 The ECC is then calculated on the resultin...

Page 323: ...Wait States Required Read Operation Read Idle 1 Pipelined read Burst read 64 bit write 2 8 16 or 32 bit write 0 read from the same address 1 read from a different address Pipelined read Read 0 Burst r...

Page 324: ...s performed on 64 bit word aligned boundaries If the write is not the entire 64 bits e g 8 16 or 32 bits a read modify write operation is generated that checks the ECC value upon the read Refer to Sec...

Page 325: ...General Purpose Static RAM SRAM PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 11 7 addi r11 r11 128 inc the ram ptr 32 GPRs 4 bytes 128 bdnz init_ram_loop loop for 80k of SRAM...

Page 326: ...General Purpose Static RAM SRAM PXN20 Microcontroller Reference Manual Rev 1 11 8 Freescale Semiconductor...

Page 327: ...rd 32 bits and page 128 bits The flash block is arranged as two functional units The first functional unit is the flash core FC The FC is composed of arrayed non volatile storage elements sense amplif...

Page 328: ...control and status registers are addressed through the slave peripheral bus Figure 12 2 Flash System Block Diagram Low address space High address space Mid address space Flash array blocks Low addres...

Page 329: ...g support and mapping based block access timing 0 31 additional cycles allowing use for emulation of other memory types Software programmable block program erase restriction control for low mid and hi...

Page 330: ...map is shown in Table 12 1 The addresses are given as an offset to the flash memory base address The flash register memory map is shown in Table 12 2 There are no program visible registers that physic...

Page 331: ...Register Memory Map Offset from FLASH_REGS_BASE 0xFFFF_8000 Register Access Reset Value Section Page 0x0000 MCR Module configuration register R W1 0x0540_0600 12 3 2 1 12 6 0x0004 LML Low Mid address...

Page 332: ...le input signature register 0 R W 0x0000_0000 12 3 2 15 12 26 0x004C UM1 User multiple input signature register 1 R W 0x0000_0000 12 3 2 15 12 26 0x0050 UM2 User multiple input signature register 2 R...

Page 333: ...o a 0 by writing a 1 to the register location A write of 0 has no effect 0 Reads are occurring normally 1 A Read While Write Error occurred during a previous read SBC Single Bit Correction SBC provide...

Page 334: ...f PGM ends the program sequence PGM can be set only under one of the following conditions User mode read ERS is low and UTE is low Erase suspend ERS and ESUS are 1 with EHV low PGM can be cleared by t...

Page 335: ...is low ESUS is cleared on reset 0 Erase sequence is not suspended 1 Erase sequence is suspended EHV Enable High Voltage The EHV bit enables the flash module for a high voltage program erase operation...

Page 336: ...the bits The bit changing priorities are detailed in Table 12 4 If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level is written Setting t...

Page 337: ...the status of enabled and is enabled until a reset operation occurs For LME the password 0xA1A1_1111 must be written to the LML register 0 Low Mid Address Locks are disabled and cannot be modified 1...

Page 338: ...Likewise the lock register is not writable if a high voltage operation is suspended MLOCK is also not writeable during UTest operations when AIE is high Upon reset information from the shadow block i...

Page 339: ...0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 HLOCK W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Figure 12 5 High...

Page 340: ...may not be written or cleared and the reset value is 0 The method to set this bit is to provide a password and if the password matches the SLE bit is set to reflect the status of enabled and is enabl...

Page 341: ...ister is not writable once an interlock write is completed until MCR DONE is set at the completion of the requested operation or if a high voltage operation is suspended MSEL is also not writeable dur...

Page 342: ...0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 HSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 8 High Address Space Block Select Register HBS T...

Page 343: ...ity over single bit corrections which take priority over state machine errors This is especially valuable in the event of a RWW operation where the read senses an ECC error or single bit correction an...

Page 344: ...und robin modes write requests are prioritized higher than read requests and read requests are prioritized higher than speculative prefetch requests whenever both ports issue concurrent requests This...

Page 345: ...roper flash operation This field is set to 0b11 by hardware reset 00 No additional wait states are added 01 One additional wait state is added 10 Two additional wait states are added 11 Three addition...

Page 346: ...and all buffer valid bits are cleared 1 The line read buffers are enabled to satisfy read requests on hits Buffer valid bits may be set when the buffers are successfully filled Offset FLASH_REGS_BASE...

Page 347: ...HSACC field to determine the final flash attributes SHDACC 7 4 Shadow Block Data Access Control This bit field defines code data access control for each 4 KByte sector within the shadow block region o...

Page 348: ...his field is initialized by hardware reset to the value contained in address 0x3E08 of the shadow block of the flash array An erased or unprogrammed flash sets this field to 0xFFFF_FFFF Table 12 14 S...

Page 349: ...12 13 PFlash Data Access Control Register PFSACC Table 12 15 PFlash Data Access Control Register PFDACC Field Descriptions Field Description DACC 31 0 Data Access Control This bit field defines code...

Page 350: ...ignals created by the c90fl module see c90fl Integration Guide ECC corrections that occur when SBCE is cleared will not be logged 0 Single Bit Corrections observation is disabled 1 Single Bit Correcti...

Page 351: ...AIE 1 it may be terminated by clearing AIE if the operation has finished AID 1 or aborted by clearing AIE if the operation is ongoing AID 0 AIE is not simultaneously writable to a 1 as UTI is being c...

Page 352: ...y integrity checks The DAI 63 32 correspond to the 32 Array bits representing Word 1of the double word selected in the ADR register Offset FLASH_REGS_BASE 0x0048 Access User read write 0 1 2 3 4 5 6 7...

Page 353: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISR 143 128 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 21 User Multiple Input Signature Register 4 UM4 Table 12 19 UMn Field Descri...

Page 354: ...ead While Write RWW The flash core is divided into partitions Partitions are always comprised of two or more blocks Partitions are used to determine read while write RWW groupings While a write progra...

Page 355: ...more than one word or doubleword is to be programmed write each additional address in the page with data to be programmed This is referred to as a program data write All unwritten data words default...

Page 356: ...le to step 8 of the program sequence An aborted program results in MCR PEG being set low indicating a failed operation The data space being operated on before the abort will contain indeterminate data...

Page 357: ...nd PGM 0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM more words Step 8 No Yes Wr...

Page 358: ...g programmed erased return indeterminate data The program sequence is resumed by writing a logic 0 to MCR PSUS MCR EHV must be set to a 1 before clearing MCR PSUS to resume operation When the operatio...

Page 359: ...ves the flash core blocks being erased in an indeterminate data state This may be recovered by executing an erase on the affected blocks 12 4 1 5 Flash Erase Suspend Resume The erase sequence may be s...

Page 360: ...ode read state Write MCR ERS 1 Select blocks Erase interlock write Step 1 Step 2 Step 3 Write MCR EHV 1 High voltage active Access MCR DONE Step 4 WRITE ESUS 1 Read MCR DONE 1 Erase suspend ERS 0 User...

Page 361: ...sequence of events 1 Enable UTest mode 2 Select the block or blocks to be receive array integrity check by writing ones to the appropriate registers in LMS or HBS registers NOTE Locked Blocks can be...

Page 362: ...IS has no effect and the reads will be done sequentially The data to be read is customer specific Thus a customer can provide user code into the flash and the correct MISR value is calculated The cust...

Page 363: ...R PEAS 1 only After the user has begun an erase operation on the shadow block the operation cannot be suspended to program the main address space and vice versa The user must terminate the shadow eras...

Page 364: ...leep during a program or erase high voltage operation the appropriate suspend bit is set to a 1 The user may resume the program or erase operation at the time the module is enabled by clearing the app...

Page 365: ...ible with the original Power PC user instruction set architecture UISA However in the Power Architecture definition the original floating point resources used by a SIMD design supporting single precis...

Page 366: ...nits Multi ported register file capable of sustaining three read and two write operations per clock CPU Control Logic Load 32 KB Cache Data Memory Management Unit Address Store Unit Control Instructio...

Page 367: ...riable Length Encoding APU providing improved code density 13 1 3 Features The following is a list of some key features of the e200z6 Single issue 32 bit CPU built on the Power Architecture embedded c...

Page 368: ...operations 32 bit priority encoder for count leading zeros function 32 bit single cycle barrel shifter for static shifts and rotates 32 bit mask unit for data masking and insertion Divider logic for...

Page 369: ...instructions The integer execution unit consists of a 32 bit arithmetic unit AU a logic unit LU a 32 bit barrel shifter shifter a mask insertion unit MIU a condition register manipulation unit CRU a c...

Page 370: ...ply divide compare and conversion operations are provided and most operations can be pipelined 13 2 Core Registers and Programmer s Model This section describes the registers implemented in the e200z6...

Page 371: ...308 SPR 309 SPR 310 SPR 561 Instruction Address Compare IAC1 IAC2 IAC3 IAC4 SPR 312 SPR 313 SPR 314 SPR 315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200z6 specific registers may not be...

Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...

Page 373: ...ndition Register CR Count Register SPR 9 CTR Link Register SPR 8 LR XER SPR 1 XER Timers Time Base read only TBL SPR 268 TBU SPR 269 SPRG4 SPRG5 SPRG6 SPRG7 SPR 260 SPR 261 SPR 262 SPR 263 SPR General...

Page 374: ...ER indicates overflow and carries for integer operations Link register LR The LR provides the branch target address for the branch conditional to link register bclr bclrl instructions and is used to h...

Page 375: ...is set to the effective address EA generated by the faulting instruction Software use special purpose registers SPRGs The SPRG0 SPRG7 registers are provided for operating system use Exception syndrom...

Page 376: ...menting counter that provides a mechanism for causing a decrementer exception after a programmable delay Decrementer auto reload DECAR This register is provided to support the auto reload feature of t...

Page 377: ...handler for different classes of interrupts Debug facility registers Debug control register 3 DBCR3 controls for debug functions not described in the Power Architecture embedded category Debug counte...

Page 378: ...n Disabled events The unconditional debug event UDE is not supported Power management e200z6 core halted state and stopped state are not supported Power management The following low power modes are no...

Page 379: ...f the MSR bit MSR IS or MSR DS is compared to the number of bits of the EPN field and the TS field of TLB entries If the contents of the effective address plus the address space bit matches the EPN fi...

Page 380: ...Figure 13 5 shows the effective to real address translation flow Figure 13 5 Effective to Real Address Translation Flow 13 3 1 4 Permissions The application software can restrict access to virtual pa...

Page 381: ...ile in user mode UX User execute permission Allows instruction fetches to access the page and instructions to be executed from the page while in user mode If the translation match was successful the p...

Page 382: ...B1 NV Next replacement victim for TLB1 software managed Software updates this field it is copied to the ESEL field on a TLB error SPR 625 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17...

Page 383: ...31 R EPN VL E W I M G E W Reset Undefined on Power Up Unchanged on Reset Figure 13 9 MMU Assist Register 2 MAS 2 Table 13 6 MAS 2 EPN and Page Attributes Field Description EPN Effective page number 0...

Page 384: ...ccessed in big endian byte order 1 The page is accessed in true little endian byte order SPR 627 Access Read write Permission Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2...

Page 385: ...sed to index the cache array The MMU provides the virtual to physical translation for use in performing the cache tag compare If the physical address matches a valid cache tag entry the access hits in...

Page 386: ...Figure 13 13 e200z6 Unified Cache Block Diagram 13 3 2 1 Cache Organization The e200z6 cache is organized as 4 or 8 ways of 128 sets with each line containing 32 bytes four doublewords plus parity of...

Page 387: ...gister During a cache line fill doublewords received from the bus are placed into a cache linefill buffer and can be forwarded streamed to the CPU if such a request is pending Accesses from the CPU fo...

Page 388: ...s A 20 26 are used to select one cache set A set is defined as the grouping of four or eight lines one from each way corresponding to the same index into the cache array 2 The higher order physical ad...

Page 389: ...in restrictions must be followed and the ability to lock by way is no longer functional since a locked way would never be accessed When setting WAM to 1 restrictions are required to avoid coherency is...

Page 390: ...0 Bit 1 corresponds to way 1 Bit 2 corresponds to way 2 Bit 3 corresponds to way 3 The WID and WDD bits can be used for locking ways of the cache and also are used in determining the replacement poli...

Page 391: ...e from an optional MMU is ignored and all writes are treated as writethrough required When set write accesses are performed in copyback mode unless the W page attribute from an optional MMU is set 12...

Page 392: ...writing 0 to this bit location 30 CINV Cache invalidate 0 No cache invalidate 1 Cache invalidation operation When written to a 1 a cache invalidation operation is initiated by hardware After this is c...

Page 393: ...e L1FINV0 spr 5 6 Reserved read as zeros 7 8 CBSIZE Cache block size 00 The cache implements a block size of 32 bytes 9 10 CREPL Cache replacement policy 10 The cache implements a pseudo round robin r...

Page 394: ...oint unavailable IVOR 7 SRR 0 1 MSR FP 0 and attempt to execute a Book E floating point operation System call IVOR 8 SRR 0 1 Execution of the system call sc instruction AP unavailable IVOR 9 SRR 0 1 U...

Page 395: ...SSR 0 1 Debugger when HIDO DAPUEN 0 Caused by trap instruction address compare data address compare instruction complete branch taken return from interrupt interrupt taken debug counter external debug...

Page 396: ...n also be used to perform scalar operations by ignoring the results of the upper 32 bit half of the register file Some instructions are defined that produce a 64 bit scalar result Vector fixed point i...

Page 397: ...of a wait instruction places the e200z6 in the waiting state It can be used for power reduction in a interrupt based system when the core has no processing tasks An internal output signal from the cor...

Page 398: ...her information see the following documents e200z6 PowerPCTM Core Reference Manual PowerPCTM Microprocessor Family The Programming Environment for 32 bit Microprocessors Book E Enhanced PowerPCTM Arch...

Page 399: ...eneral purpose registers GPRs NOTE On the PXN20 family the e200z0 core runs at half the system clock frequency Unless otherwise noted in this chapter all stated clock delays are relative to the e200z0...

Page 400: ...CRU a Count Leading Zeros unit CLZ an 8x32 Hardware Multiplier array result feed forward hardware and a hardware divider Arithmetic and logical operations are executed in a single cycle with the excep...

Page 401: ...nd autovectored interrupts are supported by the CPU Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead Figur...

Page 402: ...data memory address calculations Pipelined operation supports throughput of one load or store operation per cycle 32 bit interface to memory 14 2 4 e200z0 System Bus Features The features of the e200z...

Page 403: ...Architecture Book E Specification The Power Architecture Book E defines register to register operations for all computational instructions Source data for these instructions are accessed from the on...

Page 404: ...3 SPR 314 SPR 315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers defined by the Power A...

Page 405: ...ribed in the Section 14 3 2 e200 Specific Special Purpose Registers 14 3 1 1 User Level Registers The user level registers can be accessed by all software with either user or supervisor privileges The...

Page 406: ...level registers Processor Control Registers Machine State Register MSR The MSR defines the state of the processor The MSR can be modified by the Move to Machine State Register mtmsr System Call se_sc...

Page 407: ...MSR on non critical interrupts and to restore machine state when se_rfi executes Critical Save Restore Register 1 CSRR1 The CSRR1 register is used to save machine state from the MSR on critical interr...

Page 408: ...ter is used to save the address of the instruction at which execution continues when se_rfdi executes at the end of a debug interrupt handler routine Debug Save Restore register 1 DSRR1 When enabled t...

Page 409: ...alue Nexus registers are not accessible by code running in User or Supervisor mode Nexus registers can be accessed only by external tools via the Nexus port Debug Table 14 3 Exceptions and Conditions...

Page 410: ...m Interrupt Interrupt Taken External Debug Event Unconditional Debug Event Reserved IVOR 16 31 1 Autovectored External and Critical Input interrupts use this IVOR Vectored interrupts supply an interru...

Page 411: ...s debug event signals processor state information Nexus OnCE JTAG interface signals and a test interface The memory portion of the e200 core interface is comprised of a 32 bit wide system bus and a un...

Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...

Page 413: ...ti core systems for implementing semaphores and provide a simple mechanism to achieve lock unlock operations via a single write access This approach eliminates architecture specific implementations li...

Page 414: ...ort for 16 hardware enforced gates in a dual processor configuration Each hardware gate appears as a three state 2 bit state machine with all 16 gates mapped as an array of bytes Three state implement...

Page 415: ...ot support any special modes of operation 15 2 Signal Description The semaphores module does not include any external signals 15 3 Memory Map and Registers This section provides a detailed description...

Page 416: ...x00 15 3 2 1 15 4 0x000B SEMA4_Gate11 Semaphores gate 11 R W 0x00 15 3 2 1 15 4 0x000C SEMA4_Gate12 Semaphores gate 12 R W 0x00 15 3 2 1 15 4 0x000D SEMA4_Gate13 Semaphores gate 13 R W 0x00 15 3 2 1 1...

Page 417: ...its execution to the original lock function The optional notification interrupt function consists of two registers for each processor an interrupt notification enable register SEMA4_CPnINE and the in...

Page 418: ...pecifies a protocol where the locking processor must unlock the gate it is recognized that system operation may require a reset function to re initialize the state of any gate s without requiring a sy...

Page 419: ...A4_RSTGT RSTGDP is the logical complement of the first data pattern 0x1D and the lower byte SEMA4_RSTGT RSTGTN specifies the gate s to be reset This gate field can specify a single gate be cleared or...

Page 420: ...enerate the specified gate reset s After the reset is performed this machine returns to the idle waiting for first data pattern write state 11 This state encoding is never used and therefore reserved...

Page 421: ...omplement of the first data pattern 0xb8 and the lower byte SEMA4_RSTNTF RSTNTN specifies the notification s to be reset This field can specify a single notification be cleared or that all notificatio...

Page 422: ...r the second data pattern write 10 The two write sequence has completed Generate the specified notification reset s After the reset is performed this machine returns to the idle waiting for first data...

Page 423: ...ed bus multiprocessors since the bus is the only path to memory The processor that gets the bus locks out all the other processors from memory If the CPU and bus provide an atomic swap operation progr...

Page 424: ...pdate the same location then the following sequence may occur 1 The Z0 locks the semaphore updates the memory unlocks the semaphore and generates a software interrupt to the Z6 2 Before the Z6 takes t...

Page 425: ...ne CP2_LOCK 2 void gateLock n int n gate number to lock int i int current_value int locked_value i processor_number obtain logical CPU number if i 0 locked_value CP0_LOCK else locked_value CP1_LOCK re...

Page 426: ...A4_ CPnNTF are required There is no required negation of the failed lock write notification interrupt as the request is automatically negated by the semaphores module once the gate has been successful...

Page 427: ...orts 16 1 1 Block Diagram Figure 16 1 shows a block diagram of the crossbar switch Figure 16 1 AXBS Block Diagram 16 1 2 AXBS Controller Configuration The AMBA Crossbar Switch AXBS supports six master...

Page 428: ...sed on a fixed priority A round robin priority mode also is available In this mode requesting masters are treated with equal priority and are granted access to a slave port in round robin fashion base...

Page 429: ...AXBS operation in debug mode is identical to operation in normal mode 16 2 Memory Map and Register Definition The memory map for the AXBS program visible registers is shown in Table 16 3 Table 16 3 A...

Page 430: ...ed 0x0210 XBAR_SGPCR2 General Purpose Control Register Slave Port 2 R W 0x0000_0000 16 2 1 2 16 6 0x0214 0x02FF Reserved 0x0300 XBAR_MPR3 Master Priority Register Slave Port 3 R W 0x5400_3210 16 2 1 1...

Page 431: ...0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 MSTR3 0 MSTR2 0 MSTR1 0 MSTR0 W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 16 2 Master Priority Registers XBAR_MPRn Table 16 4 XBAR_MPRn...

Page 432: ...ssed in supervisor mode with 32 bit accesses After the RO read only bit is set in the XBAR_SGPCR the XBAR_SGPCR and the XBAR_MPR can only be read Attempts to write to them have no effect and results i...

Page 433: ...not be written attempted writes have no effect and result in an error response ARB Arbitration mode Used to select the arbitration policy for the slave port This field is initialized by hardware reset...

Page 434: ...on examines data throughput from the point of view of masters and slaves detailing when the AXBS stalls masters or inserts bubbles on the slave side Address AXBS_BASE 0x0F00 XBAR_MGPCR7 Access Supervi...

Page 435: ...it is targeting the master remains in control of that slave port until it gives up the slave port by running an IDLE cycle leaves that slave port for its next access or loses control of the slave por...

Page 436: ...r which does not own the slave port is granted access after a one clock delay The only other time the AXBS has control of the slave port is when no masters are making access requests to the slave port...

Page 437: ...e of arbitration in round robin mode assume the three masters have ID s 0 1 and 2 If the last master of the slave port was master 1 and masters 0 and 2 make simultaneous requests they are serviced in...

Page 438: ...OL mode is selected then the slave port parks on the last master to access it passing that master s signals through to the slave bus When the master accesses the slave port again no other arbitration...

Page 439: ...IPS slave interface signals This interface is meant for slave peripherals only AIPS lite supports 32 bit IPS peripherals Byte halfword and word reads and write are supported to each Read and write acc...

Page 440: ...l within the address space of the AIPS lite are decoded to provide individual module selects for peripheral devices on the peripheral bus interface See the peripherals section of Table 2 1 for a descr...

Page 441: ...l rights are allowed to complete but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response The MPU implements a set of pro...

Page 442: ...set thus no access restrictions are enforced Table 18 1 Master Assignments and Master IDs AXBS Port AXBS Module Master ID M0 Z6 Core 0 Z6 Nexus 8 M1 eDMA 2 M2 Off Platform MLB 5 M3 FEC 4 M6 Off Platfo...

Page 443: ...protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit in the event of an access error the...

Page 444: ...18 8 0x0410 MPU_RGD1 MPU region descriptor 1 R W 1 18 3 2 4 18 8 0x0420 MPU_RGD2 MPU region descriptor 2 R W 1 18 3 2 4 18 8 0x0430 MPU_RGD3 MPU region descriptor 3 R W 1 18 3 2 4 18 8 0x0440 MPU_RGD...

Page 445: ...nate access control 8 W 1 18 3 2 5 18 13 0x0824 MPU_RGDAAC9 MPU RGD alternate access control 9 W 1 18 3 2 5 18 13 0x0828 MPU_RGDAAC10 MPU RGD alternate access control 10 W 1 18 3 2 5 18 13 0x082C MPU_...

Page 446: ...mains set A find first one instruction or equivalent can be used to detect the presence of a captured error 0 The corresponding MPU_EARn MPU_EDRn registers do not contain an unread captured error 1 Th...

Page 447: ...MPU_BASE 0x0028 MPU_EAR3 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EADDR W Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EADDR W Reset Figure 18 4 MPU Error Address Regi...

Page 448: ...qualified access control vector is captured in this field If the MPU_EDRn register contains a captured error and the EACD field is all zeroes this signals an access that did not hit in any region desc...

Page 449: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SRTADDR 0 0 0 0 0 W Reset Figure 18 6 MPU Region Descriptor Word 0 Register MPU_RGDn Word0 Table 18 6 MPU_RGDn Word0 Field Descriptions Field Descript...

Page 450: ...ify a data reference versus an instruction fetch and the operating mode supervisor user of the requesting processor For non processor data movement engines bus masters 4 7 the evaluation logic simply...

Page 451: ...The M2UM field consists of three independent bits enabling read write and execute permissions r w x If set the bit allows the given access type to occur if cleared an attempted access of that mode may...

Page 452: ...software may adjust the access controls within a region descriptor MPU_RGDn Word2 only as different tasks execute an alternate programming view of this 32 bit entity is provided If only the access con...

Page 453: ...urrent access hits in the region descriptor This field is combined with the PIDMASK and included in the region hit determination if MPU_RGDn Word2 MxPE is set Note Master ID 0 is only able to drive th...

Page 454: ...r mode The M2SM field is defined as 00 r w x read write and execute allowed 01 r x read and execute allowed but no write 10 r w read and write allowed but no execute 11 Same access controls as that de...

Page 455: ...the actual access evaluation macro but a generalized block diagram showing the major functions included in this logic block M0SM Bus Master 0 Supervisor Mode Access Control This 2 bit field defines th...

Page 456: ...dn pid 0 7 rgdn pidmask 0 7 where the current_pid is the selected process identifier from the current bus master and rgdn pid and rgdn pidmask are the appropriate process identifier fields from the re...

Page 457: ...single region descriptor and that region signals a protection violation a protection error is reported 3 If the access hits in multiple overlapping regions and all regions signal protection violations...

Page 458: ...tch instantaneously to the new value as the IPS write completes 3 If the region s start and end addresses are to be changed this would typically be performed by writing a minimum of three words of the...

Page 459: ...ovides read write access to CP0 only The overlapping space between RGD2 and RGD3 defines a shared data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR of t...

Page 460: ...Memory Protection Unit MPU PXN20 Microcontroller Reference Manual Rev 1 18 20 Freescale Semiconductor...

Page 461: ...ble ECC error is generated when two or more bits in a 64 bit doubleword are incorrect Non correctable ECC errors cause an interrupt and if enabled additional error details are available in the ECSM Er...

Page 462: ...egister R W 0x00 19 2 2 3 19 6 8 0x004A EEGR ECC error generation register R W 0x0000 19 2 2 4 19 7 16 0x0050 PFEAR PFlash ECC address register RO U 19 2 2 5 19 9 32 0x0056 PFEMR PFlash ECC master reg...

Page 463: ...ntrols FEC burst optimization behavior on the system bus Other FEC registers are described in Section 25 3 4 3 Ethernet Interrupt Mask Register EIMR through Section 25 3 4 24 Receive Buffer Size Regis...

Page 464: ...3 h5 FXSBE6 Burst enable for haddr 31 29 3 h6 FXSBE7 Burst enable for haddr 31 29 3 h7 RBEN Global read burst enable from XBAR slave port designated by FXSBEn 0 Read bursting from all XBAR slave port...

Page 465: ...ingle bit RAM correction generates an ECSM ECC interrupt request as signalled by the assertion of ESR PR1BC The address attributes and data are also captured in the PREAR PRESR PREMR PREAT and PREDR r...

Page 466: ...If the two values are different repeat from step one 4 When the values are identical write a 1 to the asserted ESR flag to negate the interrupt request See Figure 19 3 and Table 19 5 for the ECC statu...

Page 467: ...rminated with an error response See Figure 19 4 and Table 19 6 for the ECC error generation register definition PRNCE Platform RAM Non Correctable Error The occurrence of a properly enabled non correc...

Page 468: ...atform RAM single 1 bit data inversion is generated 1 One 1 bit data inversion in the platform RAM is generated FRCNCI Force Platform RAM Continuous Noncorrectable Data Inversions The assertion of thi...

Page 469: ...jection Select Platform RAM Error Injection Select The platform contains two platform RAM blocks with ECC This bit selects which RAM is injected 0 PRAM0 is injected 1 PRAM1 is injected ERRBIT Error Bi...

Page 470: ...register for capturing the AXBS bus master attributes of the last properly enabled ECC event in the platform flash memory Depending on the state of the ECC configuration register an Offset ECSM_BASE_...

Page 471: ...the platform flash causes the address attributes and data associated with the access to be loaded into the PFEAR PFEMR PFEAT and PFEDR registers and also the appropriate flag PF1BC or PFNCE in the ECC...

Page 472: ...R definition Offset ECSM_BASE_ADDR 0x0058 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PFEDR 0 15 W Reset U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...

Page 473: ...9 20 21 22 23 24 25 26 27 28 29 30 31 R PREAR W Reset U U U U U U U U U U U U U U U U Figure 19 10 Platform RAM ECC Address PREAR Register Table 19 11 PREAR Field Descriptions Field Description PREAR...

Page 474: ...PRESR 0 7 Data Bit in Error PRESR 0 7 Data Bit in Error PRESR 0 7 Data Bit in Error 0x00 No Error 0x4F DATA 32 0xA4 DATA 41 0x01 ECC 0 0x52 DATA 34 0xA7 DATA 42 0x02 ECC 1 0x54 DATA 35 0xA8 DATA 43 0x...

Page 475: ...to be asserted This register is read only any attempted write is ignored See Figure 19 13 and Table 19 15 for the platform RAM ECC attributes register definition Offset ECSM_BASE_ADDR 0x0066 Access Us...

Page 476: ...ed on a multi bit non correctable ECC error is undefined This register is read only any attempted write is ignored See Figure 19 15 and Table 19 16 for the platform RAM ECC data register definition SI...

Page 477: ...U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PREDR48 63 W Reset U U U U U U U U U U U U U U U U Figure 19 15 Platform RAM ECC Data Low PREDRL Register Table 19 16 PREDR Field Descripti...

Page 478: ...Error Correction Status Module ECSM PXN20 Microcontroller Reference Manual Rev 1 19 18 Freescale Semiconductor...

Page 479: ...tem clocks and hence offers an improved level of safety since supporting only a single clock source eliminates any risk of incorrect clock selection The SWT is reset in Sleep mode The user can select...

Page 480: ...rs are read only 20 3 1 Memory Map The SWT memory map is shown in Table 20 1 20 3 2 Register Descriptions The following sections detail the individual registers within the SWT 20 3 2 1 SWT Control Reg...

Page 481: ...e Sequence the fixed sequence 0xA602 0xB480 is used to service the watchdog 1 Keyed Service Mode two pseudorandom key values are used to service the watchdog RIA Reset on Invalid Access 0 Invalid acce...

Page 482: ...atchdog timer to be stopped when the device enters debug mode 0 SWT counter continues to run in debug mode 1 SWT counter is stopped in debug mode WEN Watchdog Enabled 0 SWT is disabled 1 SWT is enable...

Page 483: ...Time Out Register SWT_TO Table 20 4 SWT_TO Register Field Descriptions Field Description WTO Watchdog time out period in clock cycles An internal 32 bit down counter is loaded with this value or 0x010...

Page 484: ...0 0 0 0 0 0 W WSC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 5 SWT Service Register SWT_SR Table 20 6 SWT_SR Field Descriptions Field Description WSC Watchdog Service Code This field is used to...

Page 485: ...matically after reset is released Some devices can be configured to clear this bit automatically during the boot process Table 20 7 SWT_CO Register Field Descriptions Field Description CNT Watchdog Co...

Page 486: ...iod There is no timing requirement between the two writes and the service sequence logic ignores unlock sequence writes If the SWT_CR KEY bit is zero the fixed sequence 0xA602 0xB480 is written to the...

Page 487: ...second consecutive time out the SWT generates a system reset The interrupt is indicated by the time out interrupt flag SWT_IR TIF The interrupt request is cleared by writing a one to the SWT_IR TIF bi...

Page 488: ...Software Watchdog Timer SWT PXN20 Microcontroller Reference Manual Rev 1 20 10 Freescale Semiconductor...

Page 489: ...Four 32 bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode 21 1 2 Modes of Operation The STM supports two device modes of operation normal and debu...

Page 490: ...0010 STM_CCR0 STM Channel 0 Control Register R W 0x0000_0000 21 3 2 3 21 4 0x0014 STM_CIR0 STM Channel 0 Interrupt Register R W 0x0000_0000 21 3 2 4 21 4 0x0018 STM_CMP0 STM Channel 0 Compare Register...

Page 491: ...Description CPS Counter Prescaler Selects the clock divide value for the prescaler 1 256 0x00 Divide system clock by 1 0x01 Divide system clock by 2 0xFF Divide system clock by 256 FRZ Freeze Allows t...

Page 492: ...0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 3 STM Channel Sta...

Page 493: ...oundary The STM has four identical compare channels Each channel includes a channel control register STM_CCRn a channel interrupt register STM_CIRn and a channel compare register STM_CMPn The channel...

Page 494: ...System Timer Module STM PXN20 Microcontroller Reference Manual Rev 1 21 6 Freescale Semiconductor...

Page 495: ...array of timers that can be used to initiate interrupts and trigger DMA channels 22 1 1 Block Diagram A simplified block diagram of the PIT illustrates the functionality and interdependence of major...

Page 496: ...l functional parts of the PIT module are running In halt mode bit 7 1 in the SIU_HLT0 register and the clock to the PIT module is disabled halting the module 22 2 Signal Description 22 2 1 External Si...

Page 497: ...Register R W 0x0000_0000 22 3 2 2 22 5 0x0124 CVAL3 Timer 3 Current Value Register R W 0x0000_0000 22 3 2 3 22 5 0x0128 TCTRL3 Timer 3 Control Register R W1 0x0000_0000 22 3 2 4 22 6 0x012C TFLG3 Tim...

Page 498: ...ag Register R W1 0x0000_0000 22 3 2 5 22 7 Timer Channel 8 0x0170 LDVAL8 Timer 8 Load Value Register R W 0x0000_0000 22 3 2 2 22 5 0x0174 CVAL8 Timer 8 Current Value Register R W 0x0000_0000 22 3 2 3...

Page 499: ...00 LDVAL2 0x0110 LDVAL3 0x0120 LDVAL4 0x0130 LDVAL5 0x0140 LDVAL6 0x0150 LDVAL7 0x0160 LDVAL8 0x0170 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TSV31 TSV30 TSV29 TSV28 TSV27 TSV26...

Page 500: ...VL5 TVL4 TVL3 TVL2 TVL1 TVL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 4 Timer n Current Value Register CVALn Table 22 5 CVALn Field Descriptions Field Description TVLn Current Timer Value The...

Page 501: ...ed 1 Timer is active Offset Channel_base 0x000C LDVAL1 0x010C LDVAL2 0x011C LDVAL3 0x012C LDVAL4 0x013C LDVAL5 0x014C LDVAL6 0x015C LDVAL7 0x016C LDVAL8 0x017C Access User read write 0 1 2 3 4 5 6 7 8...

Page 502: ...sters A new interrupt can be generated only after the previous one is cleared If desired the current counter value of the timer can be read via the CVALn registers The counter period can be restarted...

Page 503: ...mple Configuration In the example configuration The PIT clock has a frequency of 50 MHz Timer 1 creates an interrupt every 5 12 ms Timer 8 creates a trigger event every 30 ms First the PIT module need...

Page 504: ...lowing example code matches the described setup turn on PIT PIT_REG_P pit_CTRL 0x00 Timer 1 PIT_REG_P pit_LDVAL1 0x0003E7FF setup Timer 1 for 256000 cycles PIT_REG_P pit_TCTRL1 1 1 enable Timer 1 inte...

Page 505: ...ays disabled sources Four sources are always enabled and generate a DMA request as soon as that source is selected One source the default for all channels is always disabled 23 1 1 Block Diagram A sim...

Page 506: ...iod of a DMA trigger for example Normal mode In this mode a DMA source such as SCI transmit or SCI receive for example is routed directly to the specified DMA channel The operation of the DMA_MUX in t...

Page 507: ...Channel 10 configuration R W 0x00 23 3 2 1 23 4 0x000B CHCONFIG11 Channel 11 configuration R W 0x00 23 3 2 1 23 4 0x000C CHCONFIG12 Channel 12 configuration R W 0x00 23 3 2 1 23 4 0x000D CHCONFIG13 C...

Page 508: ...L DMA Channel Enable ENBL enables the DMA channel 0 DMA channel is disabled This mode is primarily used during configuration of the DMA_MUX The DMA has separate channel enables disables which should b...

Page 509: ...I_C LINSTAT1 TXRDY SCI_C combined DMA request of the transmit data register empty transmit complete and LIN transmit data ready DMA requests SCI_C_COMBRX 0x07 SCI_C SCISR1 RDRF SCI_C LINSTAT1 RXRDY SC...

Page 510: ...17 DSPI_C DSPI_SR RFDF DSPI_C receive FIFO drain flag DSPI_F_SR_TFFF 0x18 DSPI_D DSPI_SR TFFF DSPI_D transmit FIFO fill flag DSPI_F_SR_RFDF 0x19 DSPI_D DSPI_SR RFDF DSPI_D receive FIFO drain flag eMIO...

Page 511: ...equests SCI_K_COMBTX 0x37 SCI_K SCISR1 TDRE SCI_K SCISR1 TC SCI_K LINSTAT1 TXRDY SCI_K combined DMA request of the transmit data register empty transmit complete and LIN transmit data ready DMA reques...

Page 512: ...functionality channels 0 7 of the DMA_MUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes frames or packets at fixed intervals wi...

Page 513: ...Figure 23 4 DMA_MUX Channel Triggering Normal Operation After the DMA request has been serviced the peripheral negates its request effectively resetting the gating mechanism until the peripheral re as...

Page 514: ...be configured to transfer receive data into memory effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor interventio...

Page 515: ...possible or periodically using the DMA triggering capability Doing DMA transfers from memory to memory Moving data from memory to memory typically as fast as possible sometimes with software activatio...

Page 516: ...enabled source Note that the re activation of the channel can be continuous DMA triggering is disabled or can use the DMA triggering capability In this manner it is possible to execute periodic trans...

Page 517: ...igned char DMAMUX_BASE_ADDR 0x000F volatile unsigned char CHCONFIG16 volatile unsigned char DMAMUX_BASE_ADDR 0x0010 volatile unsigned char CHCONFIG17 volatile unsigned char DMAMUX_BASE_ADDR 0x0011 vol...

Page 518: ...000A volatile unsigned char CHCONFIG11 volatile unsigned char DMAMUX_BASE_ADDR 0x000B volatile unsigned char CHCONFIG12 volatile unsigned char DMAMUX_BASE_ADDR 0x000C volatile unsigned char CHCONFIG13...

Page 519: ...volatile unsigned char CHCONFIG5 volatile unsigned char DMAMUX_BASE_ADDR 0x0005 volatile unsigned char CHCONFIG6 volatile unsigned char DMAMUX_BASE_ADDR 0x0006 volatile unsigned char CHCONFIG7 volatil...

Page 520: ...0x001C volatile unsigned char CHCONFIG29 volatile unsigned char DMAMUX_BASE_ADDR 0x001D volatile unsigned char CHCONFIG30 volatile unsigned char DMAMUX_BASE_ADDR 0x001E volatile unsigned char CHCONFI...

Page 521: ...nd destination address calculations and the actual data movement operations along with an SRAM based memory containing the transfer control descriptors TCD for the channels This implementation minimiz...

Page 522: ...execution of the minor loop Support for fixed priority and round robin channel arbitration Channel completion reported via optional interrupt requests One interrupt per channel optionally asserted at...

Page 523: ...first region defines a number of registers providing control functions however the second region corresponds to the local transfer control descriptor memory Some registers are implemented as two 32 bi...

Page 524: ...5 EDMA_CPR5 eDMA channel 5 priority register R W 0x05 24 3 2 16 24 22 8 0x0106 EDMA_CPR6 eDMA channel 6 priority register R W 0x06 24 3 2 16 24 22 8 0x0107 EDMA_CPR7 eDMA channel 7 priority register R...

Page 525: ...eDMA transfer control descriptor 01 R W 1 24 3 2 17 24 23 256 0x1040 TCD02 eDMA transfer control descriptor 02 R W 1 24 3 2 17 24 23 256 0x1060 TCD03 eDMA transfer control descriptor 03 R W 1 24 3 2 1...

Page 526: ...A transfer control descriptor 29 R W 1 24 3 2 17 24 23 256 0x13C0 TCD30 eDMA transfer control descriptor 30 R W 1 24 3 2 17 24 23 256 0x13E0 TCD31 eDMA transfer control descriptor 31 R W 1 24 3 2 17 2...

Page 527: ...nel 3 Priority EDMA_CPR3 0xFFF4_4104 eDMA Channel 4 Priority EDMA_CPR4 eDMA Channel 5 Priority EDMA_CPR5 eDMA Channel 6 Priority EDMA_CPR6 eDMA Channel 7 Priority EDMA_CPR7 0xFFF4_4108 eDMA Channel 8...

Page 528: ...and DLAST_SGA are used to compute the next TCR SADDR and TCR DADDR values When minor loop mapping is enabled EDMA_CR EMLM 1 TCDn word2 is redefined A portion of TCDn word2 is used to specify multiple...

Page 529: ...offset field and the NBYTES field The individual enable fields allow the minor loop offset to be applied to the source address the destination address or both The NBYTES field is reduced when either...

Page 530: ...s reported when the scatter gather operation begins at major loop completion A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion If a...

Page 531: ...CPE ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 3 eDMA Error Status Register EDMA_ESR Table 24 4 EDMA_ESR Field Descriptions Field Description VLD Valid Bi...

Page 532: ...recorded error was a configuration error detected in the TCD DADDR field indicating TCD DADDR is inconsistent with TCD DSIZE DOE Destination Offset Error 0 No destination offset configuration error 1...

Page 533: ...0 The state of any given channel s error interrupt enable is directly affected by writes to these registers it is also affected by writes to the EDMA_SEEIR and EDMA_CEEIR The EDMA_SEEIR and EDMA_CEEIR...

Page 534: ...return all zeroes Offset EDMA_BASE 0x0014 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EEI31 EEI30 EEI29 EEI28 EEI27 EEI26 EEI25 EEI24 EEI23 EEI22 EEI21 EEI20 EEI19 EEI18 EEI17 EEI1...

Page 535: ...nable Error Interrupt Register EDMA_SEEIR The EDMA_SEEIR provides a memory mapped mechanism to set a given bit in the EDMA_EEIRL to enable the error interrupt for a given channel The data value on a r...

Page 536: ...1 CEEI 0 provides a global clear function forcing the entire contents of the EDMA_EEIRL to be zeroed disabling error interrupts for all channels Reads of this register return all zeroes If bit 0 is s...

Page 537: ...is allows multiple byte registers to be written as a 32 bit word Reads of this register return all zeroes Table 24 10 EDMA_CEEIR Field Descriptions Field Description NOP No operation 0 Normal operatio...

Page 538: ...nism to set the START bit in the TCD of the given channel The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting bit 1 SSB 0 provide...

Page 539: ...IRQRL provides a bit map for the 32 channels signaling the presence of an interrupt request for each channel EDMA_IRQRL maps to channels 31 0 Table 24 13 EDMA_SSBR Field Descriptions Field Description...

Page 540: ...nel EDMA_ERL maps to channels 31 0 The DMA engine signals the occurrence of a error condition by setting the appropriate bit in this register The outputs of this register are enabled by the contents o...

Page 541: ...rror indicator for a single channel can be cleared 24 3 2 15 DMA Hardware Request Status EDMA_HRSL The EDMA_HRSL registers provide a bit map for the implemented channels 32 to show the current hardwar...

Page 542: ...rarily suspended in favor of starting a higher priority channel After the preempting channel has completed all its minor loop data transfers the preempted channel is restored and resumes execution Aft...

Page 543: ...corresponding channel number for each priority register that is EDMA_CPRI0 CHPRI 0b0000 and EDMA_CPR15 CHPRI 0b1111 Figure 24 17 eDMA Channel n Priority Register EDMA_CPRn Table 24 18 EDMA_CPRn Field...

Page 544: ...Last destination address adjustment scatter gather address dlast_sga 0x1000 32 x n 0x001c Beginning major iteration count biter Channel control status Word Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 545: ...st increment addressing with the SMOD function constraining the addresses to a 0 modulo size range 37 39 0x4 5 7 SSIZE 0 2 Source data transfer size 000 8 bit 001 16 bit 010 32 bit 011 64 bit 100 Rese...

Page 546: ...major iteration count This value can be applied to restore the source address to the initial value or adjust the address to reference the next data structure 128 159 0x10 0 31 DADDR 0 31 Destination a...

Page 547: ...then Adjustment value added to the destination address at the completion of the outer major iteration count This value can be applied to restore the destination address to the initial value or adjust...

Page 548: ...us bandwidth consumed by the eDMA In general as the eDMA processes the inner minor loop it continuously generates read write sequences until the minor count is exhausted This field forces the eDMA to...

Page 549: ...n 252 0x1C 28 D_REQ Disable hardware request If this flag is set the eDMA hardware automatically clears the corresponding EDMA_ERQL bit when the current major iteration count reaches zero 0 The channe...

Page 550: ...s exhausted additional processing is performed including the final address pointer updates reloading the TCDn CITER field and a possible fetch of the next TCDn from memory as part of a scatter gather...

Page 551: ...a based on a two deep nested flow The basic flow of a data transfer can be partitioned into three segments As shown in Figure 24 19 the first segment involves the channel service request In the diagra...

Page 552: ...data is temporarily stored in the data path module until it is gated onto the system bus during the destination write This source read destination write processing continues until the inner minor byte...

Page 553: ...e final address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from memor...

Page 554: ...TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQRH and or EDMA_ERQRL registers 6 Request channel service by software setting the TCD START bit or...

Page 555: ...r gather operations if enabled Figure 24 22 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can occur after each minor loop and one leve...

Page 556: ...annel number causing the error is recorded in the EDMA_ESR If the error source is not removed before the next activation of the problem channel the error is detected and recorded again DMA request Min...

Page 557: ...termined because they reflect the undefined channel A group priority error is global and any request in any group causes a group priority error If priority levels are not unique the highest channel gr...

Page 558: ...G14_SOURCE 14 DMA_MUX CHCONFIG14 SOURCE DMA MUX channel 14 source DMA_MUX_CHCONFIG15_SOURCE 15 DMA_MUX CHCONFIG15 SOURCE DMA MUX channel 15 source DMA_MUX_CHCONFIG16_SOURCE 16 DMA_MUX CHCONFIG16 SOURC...

Page 559: ...rbitration but this time channels are serviced in channel number order One channel only is serviced from each requesting group for each round robin pass through the groups Within each group channels a...

Page 560: ...es for the destination The final source and destination addresses are adjusted to return to their beginning values TCD CITER TCD BITER 1 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE 0 TCD SLAST...

Page 561: ...are enabled in the EDMA_ERQR channel service requests are initiated by the slave device ERQR should be set after TCD Note that TCD START 0 TCD CITER TCD BITER 2 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOF...

Page 562: ...8 read_byte 0x1019 read_byte 0x101a read_byte 0x101b f write_word 0x2018 third iteration of the minor loop g read_byte 0x101c read_byte 0x101d read_byte 0x101e read_byte 0x101f h write_word 0x201c las...

Page 563: ...IVE 1 TCD DONE 0 channel is executing 3 TCD START 0 TCD ACTIVE 0 TCD DONE 0 channel has completed the minor loop and is idle or 4 TCD START 0 TCD ACTIVE 0 TCD DONE 1 channel has completed the major lo...

Page 564: ...rities are treated as equal or more exactly constantly rotating when round robin arbitration mode is selected The TCD ACTIVE bit for the preempted channel remains asserted throughout the preemption Th...

Page 565: ...l during channel execution 24 5 8 1 Dynamic Channel Linking and Dynamic Scatter Gather Operation Dynamic channel linking and dynamic scatter gather operation is the process of changing the TCD MAJOR E...

Page 566: ...successful b If the bit is cleared the attempted dynamic link did not succeed the channel was already retiring This same coherency model is true for dynamic scatter gather operations For both dynamic...

Page 567: ...nection information for both the 10 and 100 Mbps MII media independent interface as well as the 7 wire serial interface Additionally detailed descriptions of operation and the programming model are in...

Page 568: ...aces for connection to an external Ethernet transceiver The FEC supports the 10 100 Mbps MII and the 10 Mbps only 7 wire interface which uses a subset of the MII signals The descriptor controller is a...

Page 569: ...lock and receive data flows from the receive block into the receive FIFO The user controls the FEC by writing through the slave interface module into control registers located in each block The CSR co...

Page 570: ...Automatic internal flushing of the receive FIFO for runts collision fragments and address recognition rejects no system bus utilization Address recognition Frames with broadcast address may be always...

Page 571: ...the MII for a description of how to read and write registers in the transceiver via this interface 25 2 2 2 10 Mbps 7 Wire Interface Operation The FEC supports a 7 wire interface as used by many 10 M...

Page 572: ...d bits are not needed for the FEC software driver They are used mainly by the FEC subblocks for the FEC operation and happen to be visible through the slave interface Errant writes to these locations...

Page 573: ...Individual Hash Table R W U 25 3 4 15 25 23 0x011C IALR Lower 32 Bits of Individual Hash Table R W U 25 3 4 16 25 23 0x0120 GAUR Upper 32 bits of Group Hash Table R W U 25 3 4 17 25 24 0x0124 GALR Low...

Page 574: ...on some of the recommended package objects which are supported do not require MIB counters Counters for transmit and receive full duplex flow control frames are included as well Table 25 3 MIB Counter...

Page 575: ...TS RMON Rx packet count 0x0288 RMON_R_BC_PKT RMON Rx Broadcast Packets 0x028C RMON_R_MC_PKT RMON Rx Multicast Packets 0x0290 RMON_R_CRC_ALIGN RMON Rx Packets w CRC Align error 0x0294 RMON_R_UNDERSIZE...

Page 576: ...t in the interrupt mask register EIMR is also set The bit in the EIR is cleared if a one is written to that bit position writing zero has no effect This register is cleared on hardware reset These int...

Page 577: ...t occur GRA Graceful stop complete This interrupt is asserted for one of three reasons Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being...

Page 578: ...ad CRC and the remainder of the frame is discarded RL Collision retry limit This bit indicates that a collision occurred on each of 16 successive attempts to transmit the frame The frame is discarded...

Page 579: ...descriptor ring and processes transmit frames provided ECR ETHER_EN is also set Once the FEC polls a transmit descriptor whose ready bit is not set the FEC clears X_DES_ACTIVE and ceases transmit desc...

Page 580: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 5 Transmit Descriptor Active Register TDAR Table 25 7 TDAR Field Descriptions Field Description 0 6 Reserved should be cleared X_DES_ACTIVE Set to one when this r...

Page 581: ...nsmitted frame The buffer descriptors for an aborted transmit frame are not updated after clearing this bit When ETHER_EN is deasserted the DMA buffer descriptor and FIFO control logic are reset inclu...

Page 582: ...r are altered as the contents are serially shifted and are unpredictable if read by the user Once the read management frame operation has completed the MII interrupt is generated At this time the cont...

Page 583: ...write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 DIS_ PREA MBLE M...

Page 584: ...0 Receive Control Register RCR The RCR is programmed by the user The RCR controls the operational mode of the receive block and 1 Note Observe maximum system clock frequency when programming MII_SPEED...

Page 585: ...f asserted the receiver detects PAUSE frames Upon PAUSE frame detection the transmitter stops transmitting data frames for a given duration BC_REJ Broadcast frame reject If asserted frames with DA des...

Page 586: ...ed With transmission of data frames stopped the MAC transmits a MAC Control PAUSE frame Next the MAC clears the TFC_PAUSE bit and resumes transmitting data frames Note that if the transmitter is pause...

Page 587: ...n address field of receive frames with an individual DA In addition this register is used in bytes 4 and 5 of the 6 byte Source Address field when transmitting PAUSE frames Bits 16 31 of PAUR contain...

Page 588: ...set FEC_BASE 0x00E8 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PADDR2 W Reset U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TYPE W Reset 1 0 0 0...

Page 589: ...heck for possible match with the DA field of receive frames with an individual DA This register is not reset and must be initialized by the user Table 25 17 OPD Field Descriptions Field Description OP...

Page 590: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IADDR2 W Reset U U U U U U U U U U U U U U U U Figure 25 17 Descriptor Individual Lower Address IALR Table 25 19 IALR Field Descriptions Field Descrip...

Page 591: ...system bus The byte counts associated with the TFWR field may need to be modified to match a given system requirement worst case bus access latency by the transmit data DMA channel Table 25 20 GAUR F...

Page 592: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X_WMRK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 20 FIFO Transmit FIFO Watermark Register T...

Page 593: ...r descriptor queue in external memory This pointer must be 32 bit aligned however it is recommended it be made 128 bit aligned evenly divisible by 16 This register is not reset and must be initialized...

Page 594: ...he user prior to operation Offset FEC_BASE 0x0180 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R R_DES_START W Reset U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27...

Page 595: ...5 4 Functional Description This section describes the operation of the FEC beginning with the hardware and software initialization sequence then the software Ethernet driver interface for transmitting...

Page 596: ...data path is reset 25 4 2 User Initialization Prior to Asserting ECR ETHER_EN The user needs to initialize portions of the FEC prior to setting the ECR ETHER_EN bit The exact values depend on the par...

Page 597: ...nterface Options The FEC supports both an MII interface for 10 100 Mbps Ethernet and a 7 wire serial interface for 10 Mbps Ethernet The interface mode is selected by the RCR MII_MODE bit In MII mode R...

Page 598: ...gic asserts FEC_TX_EN and starts transmitting the preamble PA sequence the start frame delimiter SFD and then the frame information from the FIFO However the controller defers the transmission if the...

Page 599: ...and frame TFINT interrupts may be generated as determined by the settings in the EIMR The transmit error interrupts are HBERR BABT LATE_COL COL_RETRY_LIM and XFIFO_UN If the transmit frame length exc...

Page 600: ...FD sequence is complete In MII mode the receiver checks for at least one byte matching the SFD Zero or more PA bytes may occur but if a 00 bit sequence is detected prior to the SFD byte the frame is i...

Page 601: ...oup hash table lookup using the 64 entry hash table programmed in GAUR and GALR If a hash match occurs the receiver accepts the frame If flow control is enabled the microcontroller does an exact addre...

Page 602: ...ast REJect False True False BC_REJ 1 Frame Hash Match Exact Match Pause Frame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Fr...

Page 603: ...r If the CRC generator selects a bit that is set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group add...

Page 604: ...f ff ff 0x2 2 35 ff ff ff ff ff 0x3 3 B5 ff ff ff ff ff 0x4 4 95 ff ff ff ff ff 0x5 5 D5 ff ff ff ff ff 0x6 6 F5 ff ff ff ff ff 0x7 7 DB ff ff ff ff ff 0x8 8 FB ff ff ff ff ff 0x9 9 BB ff ff ff ff ff...

Page 605: ...ff ff ff ff ff 0x27 39 7F ff ff ff ff ff 0x28 40 4F ff ff ff ff ff 0x29 41 1F ff ff ff ff ff 0x2A 42 3F ff ff ff ff ff 0x2B 43 BF ff ff ff ff ff 0x2C 44 9F ff ff ff ff ff 0x2D 45 DF ff ff ff ff ff 0x2...

Page 606: ...nsmit backoff timer hardware which is used for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DUR slot times have e...

Page 607: ...ollision occurs during the preamble sequence the JAM pattern is sent after the end of the preamble sequence If a collision occurs within 512 bit times the retry process is initiated The transmitter wa...

Page 608: ...is asserted if enabled in the EIMR register 25 4 14 1 3 Late Collision When a collision occurs after the slot time 512 bits starting at the preamble the FEC terminates transmission All remaining buffe...

Page 609: ...ive frame length exceeds MAX_FL bytes the BABR interrupt is generated and the LG bit in the end of frame RxBD is set The frame is not truncated unless the frame length exceeds 2047 bytes 25 4 14 2 5 T...

Page 610: ...source address length type fields so this must be provided by the driver in one of the transmit buffers The Ethernet MAC can append the Ethernet CRC to the frame Whether the CRC is appended by the MAC...

Page 611: ...For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame keeping in mind that a malfunction on the network or out of spec implementation cou...

Page 612: ...promiscuous mode the user can use the M bit to quickly determine whether the frame was destined to this station This bit is valid only if the L bit is set and the PROM bit is set 0 The frame was recei...

Page 613: ...nditions and in statistic counters in the MIB block See Section 25 3 3 MIB Block Counters Memory Map for more details Offset 2 Bits 0 15 Data Length Data length Written by the FEC Data length is the n...

Page 614: ...tten by user 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR Offset 0 Bit 3 TO2 Transmit software ownership Thi...

Page 615: ...ycle length in T The actual length of a cycle in T for the ideal controller 0 ppm EBI External Bus Interface FlexRay Memory Memory Window to store message buffer payload header status and synchronizat...

Page 616: ...e CHI Protocol engine PE Clock domain crossing unit CDC A block diagram of the controller with its surrounding modules is given in Figure 26 1 NOTE The FlexRay block is not implemented on the PXN21 T...

Page 617: ...for asynchronous PE and CHI clock domains The controller stores the frame header and payload data of frames received or of frames to be transmitted in the FlexRay memory The application accesses the F...

Page 618: ...ay memory Allows for flexible and efficient message buffer implementation Consistent data access ensured by means of buffer locking scheme Application can lock multiple buffers at the same time Size o...

Page 619: ...cribes the basic operational power modes of the controller 26 1 6 1 Disabled Mode The controller enters the Disabled Mode during hard reset The controller indicates that it is in the Disabled Mode by...

Page 620: ...ignals FR_A_RX FR_A_TX and FR_A_TX_EN are available on each package option The availability of the other off chip signals depends on the package option 26 2 1 Detailed Signal Descriptions This section...

Page 621: ...bus clock Since the FlexRay protocol requires data delivery at fixed points in time the memory read cycles from the FlexRay memory must be finished after a fixed amount of time To ensure this a minimu...

Page 622: ...lock must be connected to the oscillator pins The crystal or clock must fulfill the requirements given by the FlexRay Communications System Protocol Specification Version 2 1 Rev A 26 4 2 PLL Clocking...

Page 623: ...32 Cycle Counter Register CYCTR R 0x0034 Slot Counter Channel A Register SLTCTAR R 0x0036 Slot Counter Channel B Register SLTCTBR R 0x0038 Rate Correction Value Register RTCORVR R 0x003A Offset Correc...

Page 624: ...R7 R 0x0078 Slot Status Counter Register 0 SSCR0 R 0x007A Slot Status Counter Register 1 SSCR1 R 0x007C Slot Status Counter Register 2 SSCR2 R 0x007E Slot Status Counter Register 3 SSCR3 R MTS Generat...

Page 625: ...ive FIFO Configuration continued 0x00E8 Receive FIFO System Memory Base Address High Register RFSYMBADHR R W 0x00EA Receive FIFO System Memory Base Address Low Register RFSYMBADLR R W 0x00EC Receive F...

Page 626: ...lds are not changed The condition term A or B indicates that the register or field can be written to if at least one of the conditions is fulfilled Table 26 4 Register Access Conventions Convention De...

Page 627: ...ields of the internal register remain unchanged This allows for reading back the values of the selected internal register in a subsequent read access 26 5 2 3 Module Version Register MVR This register...

Page 628: ...a system bus failure 0 Continue normal operation 1 Transition to freeze mode SCM Single Channel Device Mode This control bit defines the channel device mode of the controller as described in Section 2...

Page 629: ...rts FR_B_RX FR_B_TX and FR_A_TX_EN not driven by controller 1 0 ports FR_A_RX FR_A_TX and FR_A_TX_EN not driven by controller ports FR_B_RX FR_B_TX and FR_A_TX_EN driven by controller connected to Fle...

Page 630: ...nary OR and presented at the strobe port If no strobe signal is assigned to a strobe port the strobe port carries logic 0 For more detailed and timing information refer to Section 26 6 16 Strobe Signa...

Page 631: ...rt Select This field selects the strobe port that the strobe signal selected by the SEL is assigned to All strobe signals that are enabled and assigned to the same strobe port are combined with a bina...

Page 632: ...he first message buffer segment and the number of the last used individual message buffer Base 0x000C Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 MBSEG2DS 0 MBSEG1DS W Reset 0 0 0 0 0 0...

Page 633: ...ent correspond to the message buffer control registers MBCCSRn MBCCFRn MBFIDRn MBIDXRn with LAST_MB_SEG1 n 128 Note If LAST_MB_SEG 127 all individual message buffers belong to the first message buffer...

Page 634: ...otocol command Write Mode Command This bit controls the write mode of the POCCMD field 0 Write to POCCMD field on register write 1 Do not write to POCCMD field on register write POCCMD Protocol Contro...

Page 635: ...lag This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register CHIERFR is asserted and the chi error interrupt enable GIFER CHIE is asserted The controller gener...

Page 636: ...one of the individual transmit message buffers has the MBIF and MBIE flag asserted 1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted MIE Module Interrupt Enable Thi...

Page 637: ...such event 1 Internal protocol error detected ILCF_IF Illegal Protocol Configuration Interrupt Flag This flag is set when the protocol engine has detected an illegal protocol configuration parameter s...

Page 638: ...ss of the FlexRay protocol 0 No such event 1 pLatestTx violation occurred on channel B LTXA_IF pLatestTx Violation on Channel A Interrupt Flag This flag is set when the frame transmission on channel A...

Page 639: ...t executed For more details see Section 26 7 4 Protocol Control Command Execution 0 No such event 1 Illegal protocol control command detected PECF_IF Protocol Engine Communication Failure Interrupt Fl...

Page 640: ...terrupt request generation disabled 1 interrupt request generation enabled CSA_IE Cold Start Abort Interrupt Enable This bit controls CSA_IF interrupt request generation 0 interrupt request generation...

Page 641: ...terrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled TI1_IE Timer 1 Expired Interrupt Enable This bit controls TI1_IF interrupt request generation...

Page 642: ...e Table Written Interrupt Enable This bit controls ODT_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled Base 0x0020 Write Normal Mode 0 1...

Page 643: ...1 Search engine active while search start appears MBU_EF Message Buffer Utilization Error Flag This flag is asserted if the application writes to a message buffer control field that is beyond the num...

Page 644: ...Protocol Configuration Register 19 PCR19 0 No such error occurred 1 Static payload length error occurred NML_EF Network Management Length Error Flag This flag is set if the payload length written int...

Page 645: ...ot or segment at least Table 26 22 MBIVEC Field Descriptions Field Description TBIVEC Transmit Buffer Interrupt Vector This field provides the number of the lowest numbered enabled transmit message bu...

Page 646: ...e following slot or segment Base 0x0028 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ERRMODE SLOTMODE 0 PROTSTATE STARTUPSTATE 0 WAKEUPSTATUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 19 Protocol S...

Page 647: ...p mechanism 000 UNDEFINED 001 RECEIVED_HEADER 010 RECEIVED_WUP 011 COLLISION_HEADER 100 COLLISION_WUP 101 COLLISION_UNKNOWN 110 TRANSMITTED 111 reserved Base 0x002A Additional Reset CSAA CSP CPN RUN C...

Page 648: ...POC normal active state was reached from POC startup state via noisy leading cold start path HHR Host Halt Request Pending protocol related variable vPOC CHIHaltRequest This status bit is set when co...

Page 649: ...yntaxError for symbol window on channel B This status bit is set when a syntax error was detected during the symbol window on channel B 0 No such event 1 Syntax error detected MTB Media Access Test Sy...

Page 650: ...the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the Protocol Configuration Register 8 PCR8 The controller resets this counter on...

Page 651: ...s are detected in the communication slots the symbol window and the NIT 0 No boundary violation detected 1 Boundary violation detected AACA Aggregated Additional Communication on Channel A This flag i...

Page 652: ...cle Base 0x0032 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 CYCCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 24 Cycle Counter Register CYCTR Table 26 30 CYCTR Field Description...

Page 653: ...ot in the current communication cycle Base 0x0038 Additional Reset RUN Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R RATECORR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 27 Rate Correction Val...

Page 654: ...ntioned in the Global Interrupt Flag and Enable Register GIFER Base 0x003A Additional Reset RUN Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R OFFSETCORR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figur...

Page 655: ...eceive FIFO Channel A Almost Full Interrupt Flag Provides the same value as GIFER FAFAIF RBIF Receive Message Buffer Interrupt Flag This flag is set if for at least one of the individual receive messa...

Page 656: ...3 14 15 R SFEVB SFEVA SFODB SFODA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 31 Sync Frame Counter Register SFCNTR Table 26 37 SFCNTR Field Descriptions Field Description SFEVB Sync Frames Chan...

Page 657: ...ed to lock and unlock the odd cycle tables 0 No effect 1 Triggers lock unlock of the odd cycle tables CYCNUM Cycle Number This field provides the number of the cycle in which the currently locked tabl...

Page 658: ...Write only one pair of enabled Sync Frame Tables into FlexRay memory SDVEN Sync Frame Deviation Table Enable This bit controls the generation of the Sync Frame Deviation Tables The application must s...

Page 659: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 35 Sync Frame ID Acceptance Filter Value Register SFIDAFVR Table 26 41 SFIDAFVR Field Descriptions Field Description FVAL Filter Value This field defin...

Page 660: ...ter defines the length of the network management vector in bytes Table 26 43 NMVR 0 5 Field Descriptions Field Description NMVP Network Management Vector Part The mapping between the Network Managemen...

Page 661: ...eld Descriptions Field Description T2_CFG Timer T2 Configuration This bit configures the timebase mode of Timer T2 0 Timer T2 is absolute timer 1 Timer T2 is relative timer T2_REP Timer T2 Repetitive...

Page 662: ...lication modifies the value in this register while the timer is running the change becomes effective immediately and timer T1 will expire according to the changed value Base 0x005C Write Anytime 0 1 2...

Page 663: ...omes effective when the timer has expired according to the old values 26 5 2 43 Timer 2 Configuration Register 1 TI2CR1 Base 0x0060 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R R T2_CYC_VAL R...

Page 664: ...ot status selection registers SSSR0 to SSSR3 Each internal registers selects a slot or symbol window NIT whose status vector will be saved in the corresponding Slot Status Registers SSR0 SSR7 accordin...

Page 665: ...is field specifies the number of the slot whose status will be saved in the corresponding slot status registers Note If this value is set to 0 the related slot status register provides the status of t...

Page 666: ...counter is restricted to valid frames only SYF Sync Frame Restriction This bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1 0 The counter is not restr...

Page 667: ...6 55 SSR0 SSR7 Field Descriptions Field Description VFB Valid Frame on Channel B protocol related variable vSS ValidFrame channel B 0 vSS ValidFrame 0 1 vSS ValidFrame 1 SYB Sync Frame Indicator Chann...

Page 668: ...A protocol related variable vRF Header NFIndicator channel A 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUA Startup Frame Indicator Channel A protocol related variable vRF Header SuFIndica...

Page 669: ...3 Field Descriptions Field Description SLOTSTATUSCNT Slot Status Counter This field provides the current value of the Slot Status Counter Base 0x0080 Write MTE Anytime CYCCNTMSK CYCCNTVAL POC config 0...

Page 670: ...L 0 0 0 0 RSBIDX W WMD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 50 Receive Shadow Buffer Index Register RSBIR Table 26 59 RSBIR Field Descriptions Field Description WMD Write Mode This bit cont...

Page 671: ...High Register RFSYMBADHR Base 0x00EA Write Disabled Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SMBA 15 4 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 52 Receive FIFO System Memory Base...

Page 672: ...ster Receive FIFO Start Index Register RFSIR Receive FIFO Depth and Size Register RFDSR Receive FIFO Message ID Acceptance Filter Value Register RFMIDAFVR Receive FIFO Message ID Acceptance Filter Mas...

Page 673: ...0 0 0 0 0 0 0 0 0 Figure 26 56 Receive FIFO Depth and Size Register RFDSR Table 26 65 RFDSR Field Descriptions Field Description FIFO_DEPTHA FIFO_DEPTHB FIFO Depth This field defines the depth of the...

Page 674: ...10 11 12 13 14 15 R 0 0 0 0 0 0 RDIDX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 58 Receive FIFO B Read Index Register RFBRIR Table 26 67 RFBRIR Field Descriptions Field Description RDIDX Read...

Page 675: ...mask for the message ID acceptance filter of the selected FIFO For details on message ID filtering see Section 26 6 9 9 FIFO Filtering Base 0x0090 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 676: ...26 6 9 9 FIFO Filtering Base 0x0094 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 FIDRFVALA FIDRFVALB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 62 Receive FIFO Frame ID R...

Page 677: ...4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 F3MD F2MD F1MD F0MD 0 0 0 0 F3EN F2EN F1EN F0EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 65 Receive FIFO Range Filter Control Register RFRFCTR Table 2...

Page 678: ...er 0 disabled 1 Range filter 0 enabled Base 0x009C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 LASTDYNTXSLOTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 66 Last Dynamic Slot Channel A Reg...

Page 679: ...nPointOffset 1 MT 6 tss_transmitter gdTSSTransmitter gdBit 5 wakeup_symbol_rx_idle gdWakeupSymbolRxIdle gdBit 5 wakeup_symbol_rx_low gdWakeupSymbolRxLow gdBit 3 wakeup_symbol_rx_window gdWakeupSymbolR...

Page 680: ...ycle pdMaxDrift T 24 25 micro_per_cycle_max pMicroPerCycle pdMaxDrift T 26 27 micro_per_macro_nom_half round pMicroPerMacroNom 2 T 7 offset_correction_out pOffsetCorrectionOut T 9 rate_correction_out...

Page 681: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 macro_after_first_static_slot W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 69 Protocol Configuration Register 1 PCR1 Base 0x00A4 Write POC config 0 1 2 3 4 5...

Page 682: ...3 14 15 R 0 symbol_window_after_action_point macro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 74 Protocol Configuration Register 6 PCR6 Base 0x00AE Write POC config 0 1 2 3 4 5...

Page 683: ...col Configuration Register 10 PCR10 Base 0x00B6 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R key_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start W Reset 0 0 0...

Page 684: ...4 PCR14 Base 0x00BE Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R listen_timeout 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 83 Protocol Configuration Register 15 PCR15 Base 0x00...

Page 685: ...00C8 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_initial_offset_b micro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 88 Protocol Configuration Register 20 PCR2...

Page 686: ...0D2 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_per_cycle_min 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 93 Protocol Configuration Register 25 PCR25 Base 0x00D4 Write PO...

Page 687: ...DT bit and 1 to the LCKT bit no write access to the other bits is performed Base 0x00DA Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R extern_offset_ correction minislots_max W Reset 0 0 0 0...

Page 688: ...es whether the message buffer will generate an interrupt request when its MBIF flag is set 0 Interrupt request generation disabled 1 Interrupt request generation enabled Message Buffer Status DUP Data...

Page 689: ...ntrol the receive and transmit behavior of the message buffer according to Table 26 81 CCFE Cycle Counter Filtering Enable This control bit is used to enable and disable the cycle counter filtering 0...

Page 690: ...this field depends on the message buffer transfer type Receive Message Buffer This field is used as a filter value to determine if the message buffer is used for reception of a message received in a s...

Page 691: ...essage frames will be received If this happens several message buffers can never be locked by the application However if this occurs either the System Bus Communication Failure Error Flag SBCF_EF or t...

Page 692: ...buffers The physical message buffers are located in the FlexRay memory The structure of a physical message buffer is depicted in Figure 26 103 A physical message buffer consists of two fields the mess...

Page 693: ...of the slot status is provided in Section 26 6 5 2 3 Slot Status Description 26 6 2 2 Message Buffer Data Field The message buffer data field is a contiguous area of 2 byte entities This field contai...

Page 694: ...al Message Buffer Structure 26 6 3 1 1 Individual Message Buffer Segments The set of the individual message buffers can be split up into two message buffer segments using the Message Buffer Segment Si...

Page 695: ...ted message buffer header field in the FlexRay memory is determined according to Equation 26 4 SADR_MBHF RSBIR RSBIDX 10 SMBA Eqn 26 4 The length required for the message buffer data field depends on...

Page 696: ...eive FIFO A Read Index Register RFARIR Receive FIFO B Read Index Register RFBRIR The system memory base address SMBA is defined by the system memory base address register selected by the FIFO address...

Page 697: ...n configuration data for individual message buffers is located in the following registers Message Buffer Data Size Register MBDSR The MBSEG2DS and MBSEG1DS fields define the minimum length of the mess...

Page 698: ...ssociated with this message buffer 26 6 3 5 Individual Message Buffer Control Data During normal operation each individual message buffer can be controlled by the control and trigger bits CMT LCKT EDT...

Page 699: ...POP Count Register RFFLPCR 26 6 3 7 3 Receive FIFO Status Data The current status of the receive fifo is provided in the following register Global Interrupt Flag and Enable Register GIFER Receive FIF...

Page 700: ...um 64 Kbytes Each region start at a 16 byte boundary Message Buffer Header Area FlexRay Memory Message Buffer Data Area Sync Frame Table Area Data Field Offset Frame Header Slot Status Data Field Offs...

Page 701: ...6 Eqn 26 7 2 The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill Equation 26 8 SADR_MBHF i 10 SYMDARD SMBA 0 i 1024 Eqn 26 8 FIFO Header Area FIFO FlexRay Me...

Page 702: ...t fulfill Equation 26 11 SADR_MBHF i 10 RFSYMBADR SMBA 0 i 1024 Eqn 26 11 2 The message buffer header fields for each FIFO have to be a contiguous area 26 6 4 6 Message Buffer Data Area The message bu...

Page 703: ...frame received regardless of whether the frame is valid or not For transmit message buffers the application writes the frame header of the frame to be transmitted into this location The frame header w...

Page 704: ...he value of the FID field must be equal to the value of the corresponding Message Buffer Frame ID Registers MBFIDRn If the controller detects a mismatch while transmitting the frame header it will set...

Page 705: ...of the received frame stored in the message buffer CYCCNT Cycle Count This is the number of the communication cycle in which the frame stored in the message buffer was received PLDLEN Payload Length T...

Page 706: ...he slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by Table 26 87 The meaning of the...

Page 707: ...e Indicator Channel B protocol related variable vRF Header NFIndicator channel B 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUB Startup Frame Indicator Channel B protocol related variable v...

Page 708: ...r NFIndicator 1 SUA Startup Frame Indicator Channel A protocol related variable vRF Header SuFIndicator channel A 0 vRF Header SuFIndicator 0 1 vRF Header SuFIndicator 1 SEA Syntax Error on Channel A...

Page 709: ...tocol related variable vRF Header SuFIndicator channel B 0 vRF Header SuFIndicator 0 1 vRF Header SuFIndicator 1 SEB Syntax Error on Channel B protocol related variable vSS SyntaxError channel B 0 vSS...

Page 710: ...Error on Channel A protocol related variable vSS SyntaxError channel A 0 vSS SyntaxError 0 1 vSS SyntaxError 1 CEA Content Error on Channel A protocol related variable vSS ContentError channel A 0 vS...

Page 711: ...s restrictions given in Table 26 92 26 6 6 Individual Message Buffer Functional Description The controller provides three basic types of individual message buffers 1 Single Transmit Message Buffers 2...

Page 712: ...configures the size of the two segments of individual message buffers by writing the message buffer number of the last message buffer in the first segment into the LAST_MB_SEG1 field in the Message Bu...

Page 713: ...uffers A single transmit message buffer is used by the application to provide message data to the controller that will be transmitted over the FlexRay Bus The controller uses the transmit message buff...

Page 714: ...20 A description of the states is given in Table 26 96 which also provides the access scheme for the access regions The status bits MBCCSRn EDS and MBCCSRn LCKS provide the application with the requir...

Page 715: ...for Null Frame transmission HLckCCSa 1 1 MSG Locked and Slot Assigned Applications access to data control and status Message buffer assigned to next static slot CCNf 1 0 NF Null Frame Transmission He...

Page 716: ...triggered by each of these commands depends on the current value of the status bit MBCCSRn LCKS If the command triggers the lock transition HL and the message buffer is in the state CCTx the lock tra...

Page 717: ...trol Status Registers MBCCSRn The physical access to the message buffer data field is described in Section 26 6 3 1 Individual Message Buffers MA slot match and CycleCounter match Message Available Me...

Page 718: ...message buffers can be used for message transmission in the next slot The controller transmits a message from a message buffer if both of the following two conditions are fulfilled at the start of th...

Page 719: ...tatic slot S on channel A if this slot is assigned to the controller for channel A and all transmit message buffers with MBFIDRn FID S and MBCCFRn CHA 1 are either not committed MBCCSRn CMT 0 or locke...

Page 720: ...26 Null Frame Transmission from Idle state with locking 26 6 6 2 7 Message Buffer Status Update After the end of each slot the PE generates the slot status vector Depending on the this status the tran...

Page 721: ...a minislot number greater than pLatestTx 2 The transmission slot did not exist in the dynamic segment at all Additionally an incomplete message transmission can be caused by internal communication er...

Page 722: ...accessed from the application and the controller at any time controller set access has higher priority The controller restricts its access to the regions depending on the current state of the message...

Page 723: ...is 0 0 CFG Disabled Message Buffer under configuration Excluded from message buffer search HDisLck 0 1 CFG Disabled and Locked Message Buffer under configuration Excluded from message buffer search HL...

Page 724: ...on at a time There is no need to specify priorities among them As shown in Table 26 104 the module transitions have a higher priority than the application transitions For all states except the CCRx st...

Page 725: ...ion slot the received frame data are written into the shadow buffers For details on receive shadow buffers see Section 26 6 6 3 5 Receive Shadow Buffers Concept The data and status of the receive mess...

Page 726: ...er NFIndicator Update description 1 1 Valid non null frame received Message Buffer Data Field updated Frame Header Field updated Slot Status Field updated DUP 1 DVAL 1 MBIF 1 1 0 Valid null frame rece...

Page 727: ...controller will not change the content of the message buffer 26 6 6 3 5 Receive Shadow Buffers Concept The receive shadow buffer concept applies only to individual receive message buffers The intentio...

Page 728: ...he transmit side and is used by the controller to transmit the message data to the FlexRay bus The two sides are located in adjacent individual message buffers The message buffer that implements the c...

Page 729: ...in Figure 26 132 A description of the states is given in Table 26 108 The states for the transmit side of a Table 26 106 Double Transmit Message Buffer Access Regions Description Access Description Re...

Page 730: ...e commit side of a double transmit message buffer is given in Table 26 107 Table 26 107 Double Transmit Message Buffer State Description Commit Side State MBCCSR 2n Access Region Description EDS LCKS...

Page 731: ...1 0 Slot Assigned Message buffer assigned to next static slot Ready for Null Frame transmission CCSaCCITx 1 0 TX Slot Assigned and Internal Message Transfer Message buffer assigned to next static slo...

Page 732: ...commands can be issued on the commit side only Any lock or unlock command issued on the transmit side will be ignored and the double transmit buffer lock error flag DBL_EF in the CHI Error Flag Regis...

Page 733: ...to transmit side IE Internal Message Transfer End Stop transfer of message data from commit side to transmit side Note The internal message transfer is stopped before the slot or segment start transmi...

Page 734: ...er is implemented as the swapping of the content of the Message Buffer Index Registers MBIDXRn of the commit side and the transmit side After the swapping the commit side CMT bit is cleared the commit...

Page 735: ...teed that each provided message will be transmitted at least once The immediate commit mode is configured by setting the message buffer commit mode bit MCM in the Message Buffer Configuration Control...

Page 736: ...de of a double transmit message buffer is the same as for single transmit message buffers which is described in Section 26 6 6 2 7 Message Buffer Status Update Additionally the slot status field of th...

Page 737: ...ighest priority the message buffer with the lowest message buffer number is selected All message buffer which have the highest priority must have a consistent channel assignment as specified in Sectio...

Page 738: ...le Counter Filter Registers MBCCFRn defines the channels on which the message buffer will receive or transmit The message buffer with number n transmits or receives on channel A if MBCCFRn CHA 1 and t...

Page 739: ...26 6 8 1 1 Basic Type Not Changed RC1 A reconfiguration will not change the basic type of the individual message buffer if both the message buffer transfer direction bit MBCCSRn MTD and the message bu...

Page 740: ...rst FIFO entry given by Receive FIFO Start Index Register RFSIR The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth and Size Register RFDSR 26 6 9 2 FIFO Config...

Page 741: ...The FIFO periodic timer is configured via the Receive FIFO Periodic Timer Register RFPTR If the periodic timer duration RFPTIR PTD is configured to 0x0000 the periodic timer is continuously expired If...

Page 742: ...ontent In this case the application must not read data from the FIFO To access the oldest message in the FIFOA FIFOB the application first reads the read index RDIDX out of the Receive FIFO A Read Ind...

Page 743: ...FIFO B Read Index Register RFBRIR is incremented by 1 if the FIFO was not empty If the read index reaches the top of the FIFO it wraps around to the FIFO start index automatically 26 6 9 9 FIFO Filte...

Page 744: ...ue Frame ID Append to FIFO vRF Frame ID No Frame Received FIFO full Set FIFO Overflow Interrupt Flag Message Buffer Found No Passed Passed Passed Yes vRF Header NFIndicator 0 Mask Rejection Filter Ran...

Page 745: ...s are rejected no frame will pass This is the reset value for the RX FIFO 26 6 9 9 2 RX FIFO Frame ID Range Rejection Filter Each of the four RX FIFO Frame ID Range filters can be configured as a reje...

Page 746: ...payload preamble indicator bit PPI set to 1 and with the message ID MID the first two bytes of the payload will pass the RX FIFO Message ID Acceptance Filter if Equation 26 18 is fulfilled Eqn 26 18 T...

Page 747: ...ernal channel A and the FlexRay Port A is used Depending on the setting of MCR CHA and MCR CHB the internal channel A behaves either as a FlexRay Channel A or FlexRay Channel B The bit MCR CHA must be...

Page 748: ...P fields in the Protocol Operation Control Register POCR The PE applies the external correction values in the next even odd cycle pair as shown in Figure 26 142 and Figure 26 143 CHI PE cfg A reg A cC...

Page 749: ...le 2n 1 If this field is written to after the end of the static segment of cycle 2n 1 it is not guaranteed that the external correction value is applied in cycle pair 2n 2 2n 3 If the value is not app...

Page 750: ...c Frame ID ChA 5 Sync Frame ID ChA 6 Sync Frame ID ChA 7 Sync Frame ID ChA 8 Sync Frame ID ChA 9 Sync Frame ID ChA 10 Sync Frame ID ChA 11 Sync Frame ID ChA 12 Sync Frame ID ChA 13 Sync Frame ID ChA 1...

Page 751: ...n transferred into the FlexRay memory the controller sets the even table valid bit SFTCCSR EVAL and the Even Cycle Table Written Interrupt Flag EVT_IF in the Protocol Interrupt Flag Register 1 PIFR1 I...

Page 752: ...exRay memory the lock is granted immediately and the lock status bit ELKS OLKS is set If the affected table is currently written to the FlexRay memory the lock is not granted In this case the applicat...

Page 753: ...s assigned and the controller is in POC normal active a frame of the type as shown in Table 26 115 is transmitted If a transmit message buffer is configured for the key slot and a valid message is ava...

Page 754: ...ame Rejection Filtering The synchronization frame rejection filter is a comparator The compare value is defined by the Sync Frame ID Rejection Filter Register SFIDRFR A received synchronization frame...

Page 755: ...es before the strobe signal is changed These signals are listed in Table 26 12 with a positive clock offset An example waveform is given in Figure 26 147 Figure 26 147 Strobe Signal Timing type pulse...

Page 756: ...er T2 If timer T2 is configured as an absolute timer it has the same functionality timer T1 but the configuration from Timer 2 Configuration Register 0 TI2CR0 and Timer 2 Configuration Register 1 TI2C...

Page 757: ...the related slot window NIT as shown in Figure 26 148 Figure 26 148 Slot Status Vector Update NOTE The slot status for the NIT of cycle n is provided after the start of cycle n 1 cycle start slot sta...

Page 758: ...transmission starts for slots in which the module does not transmit vSS TxConflict reception ongoing while transmission starts first valid channel that has received the first valid frame received fra...

Page 759: ...slot status counter registers is updated with the value of an internal slot status counter at the start of a communication cycle The internal slot status counter is incremented if its increment condit...

Page 760: ...increment on boundary violation SSCCRn STATUSMASK 0 vSS TxConflict increment on transmission conflict 1 If the slot status counter is in single cycle mode SSCCRn MCY 0 the internal slot status counter...

Page 761: ...s Communication Failure Error Flag SBCF_EF or the Illegal System Bus Address Error Flag ILSA_EF will be set in the Controller Host Interface Error Flag Register CHIERFR The FlexRay module and the syst...

Page 762: ...es 2 FIFO interrupt sources Each of the 2 FIFO provides a Receive FIFO Almost Full Interrupt Flag The controller sets the Receive FIFO Almost Full Interrupt Flags GIFER FAFBIF GIFER FAFAIF in the Glob...

Page 763: ...rrupt request TBIRQ is generated when at least one of the individual transmit message buffers generates an interrupt request MBXIRQ n and the interrupt enable bit GIFER TBIE is asserted 26 6 20 2 3 Pr...

Page 764: ...als MBCCSRn MBIF n CHIER 15 0 16 PIFR0 15 0 16 PIFR1 15 0 16 RBIRQ CHIIRQ PRTIRQ GIFER FAFAIF FAFAIRQ GIFER WUPIF WUPIRQ GIFER RBIE MBCCSRn MTD Receive Transmit GIFER PRIE GIFER WUPIE GIFER MIE MBCCSR...

Page 765: ...of samples per bit cSamplesPerBit and the strobe offset cStrobeOffset The application configures the FlexRay channel bit rate by setting the BITRATE field in the Module Configuration Register MCR The...

Page 766: ...es the module related initialization steps after a system reset 1 Configure controller a configure the control bits in the Module Configuration Register MCR b configure the system memory base address...

Page 767: ...s MBIDXRn d configure the FIFOs e issue CONFIG_COMPLETE command via Protocol Operation Control Register POCR f wait for POC ready in Protocol Status Register 0 PSR0 After this sequence the controller...

Page 768: ...Eqn 26 32 This results in the formula given in Equation 26 33 which determines the required minimum CHI frequency for a given number of message buffers that are utilized Eqn 26 33 The minimum CHI fre...

Page 769: ...ill be removed from this vector 26 7 5 Message Buffer Search on Simple Message Buffer Configuration This sections describes the message buffer search behavior for a simplified message buffer configura...

Page 770: ...2 is assigned to both buffers Table 26 120 Transmit Buffer Configuration Register Field Value Description MBCCSRt MCM used only for double buffers MBT 0 single transmit buffer MTD 1 transmit buffer MB...

Page 771: ...ment The FlexRay protocol requires When a slot occurs if a slot is assigned to a node on a channel that node only transmits a frame on that channel if there is data ready and there is a match on relev...

Page 772: ...iconductor b for the cycles in the set 4n 2 which is assigned to the receive buffer only the receive buffer will be found and the node can receive data The receive and transmit cycles are shown in Fig...

Page 773: ...it parallel words and vice versa for transfer to system memory This module provides a MediaLB port for all MediaLB relevant signals and an application port to interface to the PXN20 The application po...

Page 774: ...the physical layer and link layer of the Media Local Bus specification interfacing to the MLB controller The MLB implements the 3 pin MLB mode and can run at speeds as fast as 1024Fs It does not impl...

Page 775: ...otocol please refer to the Media Local Bus Specification 27 1 4 Modes of Operation The byte order in which data is transferred between the MLB bus and the MLB device is always Big Endian however a mul...

Page 776: ...or 1024Fs clock input from the MLB controller Timing Assertion Negation Supports maximum frequency of 49 2 MHz with a 48 kHz sample rate MLBDAT I O MLB Data State Meaning Asserted Negated MLB data for...

Page 777: ...from MLB_BASE 0xC3F8_4000 Register Access Reset Value Section Page 0x0000 DCCR Device Control Configuration Register R W1 0x0000_0000 27 3 2 1 27 8 0x0004 SSCR System Status Configuration Register R W...

Page 778: ...guration Register R W 0x0000_0000 27 3 2 11 27 17 0x0084 CSCR4 Channel 4 Status Configuration Register R W 0x8000_0000 27 3 2 12 27 19 0x0088 CCBCR4 Channel 4 Current Buffer Configuration Register R W...

Page 779: ...Register R W 0x0000_0000 27 3 2 14 27 23 0x0100 CECR12 Channel 12 Entry Configuration Register R W 0x0000_0000 27 3 2 11 27 17 0x0104 CSCR12 Channel 12 Status Configuration Register R W 0x8000_0000 2...

Page 780: ...ocal Channel 6 Buffer Configuration Register R W 0x0803_E0C0 27 3 2 15 27 24 0x029C LCBCR7 Local Channel 7 Buffer Configuration Register R W 0x0803_E0E0 27 3 2 15 27 24 0x02A0 LCBCR8 Local Channel 8 B...

Page 781: ...512Fs supports 16 quadlets per frame 10 1024Fs supports 32 quadlets per frame 11 Reserved MLK MLB Lock When set indicates that the MLB Port is synchronized to the incoming MLB frame If MLK is clear u...

Page 782: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 SSRE SDMU SDML SDSC SDCS...

Page 783: ...indicate that the MLB Device has received the MlbScan E4h System Command The target DeviceAddress is stored in the SDCR register Detecting MlbScan generates a maskable system interrupt to system softw...

Page 784: ...30 31 R MSD 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 4 System Data Configuration Register SDCR Table 27 10 SDCR Field Descriptions Field Description MSD MLB System Data This register is...

Page 785: ...1 MLB SubCommand system interrupt is disabled SMCS System Masks Channel Scan When set this bit masks system interrupts for the MlbScan E4h System Command 0 MLB Channel Scan system interrupt is enable...

Page 786: ...e value is 0x00 MMA 7 0 MLB Device Major Revision For first release of the PXN20 the value is 0x02 MMI 7 0 MLB Device Minor Revision For first release of the PXN20 the value is 0x02 Offset MLB_BASE 0x...

Page 787: ...ress Configuration Register ABCR Table 27 14 ABCR Field Descriptions Field Description ARBA 31 16 Asynchronous Receive Base Address This base address is shared by all asynchronous RX channels and defi...

Page 788: ...s the upper 16 bits of the 32 bit system memory address for these channels CTBA 31 16 Control Transmit Base Address This base address is shared by all control TX channels and defines the upper 16 bits...

Page 789: ...date for Logical Channels 15 through 0 When set these bits indicate that hardware has generated an interrupt for the appropriate channel These bits are sticky and can only be cleared by a software wri...

Page 790: ...s logical channel 1 Disable Lost Frame Synchronization channel interrupts for this logical channel MBE Mask Buffer Error When set masks Buffer Error channel interrupts for this logical channel 0 Enabl...

Page 791: ...7 0 0x00 For Isochronous RX channels software must program IPL 7 2 to indicate the expected number of bytes per packet where IPL 1 0 always equals 0b00 A packet length of 253 bytes to 256 bytes can b...

Page 792: ...loaded by hardware with the number of valid bytes in the last packet of a broken Isochronous RX channel Used in conjunction with CCBCRn BCA IVB 1 0 can be used by software to determine the final valid...

Page 793: ...successfully transmitted or received 1 Last quadlet of the Previous Buffer has been successfully transmitted or received PBDB Previous Buffer Detect Break When set this bit indicates that either a TX...

Page 794: ...hen set this bit indicates the last quadlet of the Current Buffer has been successfully transmitted or received The setting of this bit generates a maskable channel interrupt to system software This b...

Page 795: ...BCA field marks which quadlet of the buffer is currently being processed The upper half of the beginning address of the Current Buffer is system memory is defined by SBCR SRBA ABCA ARBA CBCR CRBA or I...

Page 796: ...hen set CSCRn RDY Once processing of the Current Buffer for the logical channel is complete the BSA 15 2 field is loaded into the CCBCRn BCA 15 2 field and processing of the next buffer can begin This...

Page 797: ...CBCR6 0x029C LCBCR7 0x02A0 LCBCR8 0x02A4 LCBCR9 0x02A8 LCBCR10 0x02AC LCBCR11 0x02B0 LCBCR12 0x02B4 LCBCR13 0x02B8 LCBCR14 0x02BC LCBCR15 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 798: ...Channel n Buffer Configuration Register Field Descriptions Field Description BD 8 0 Buffer Depth This field defines the depth of the local channel buffer in the local buffer RAM in increments of 4 qu...

Page 799: ...or data transfer The MediaLB topology supports one network controller connected to one or more devices where the controller is the interface between the MediaLB devices and the MOST network The contro...

Page 800: ...ule generates 18 different interrupts which are summarized in Table 27 24 For more information on interrupts please seeChapter 10 Interrupts and Interrupt Controller INTC Table 27 23 Minimum MediaLB S...

Page 801: ...The status of the Current Buffer is reflected in CSCRn STS 3 0 The Previous Buffer is the system memory buffer the DMA Controller completed processing prior to the Current Buffer The status of the Pr...

Page 802: ...of each local channel buffer is defined by the default after reset start address of each local channel buffer LCBCRn SA 8 0 The start address is the location of the beginning of the buffer in the loc...

Page 803: ...y requests based on round robin arbitration of current low priority requests and routing data and control information between channels and the Host Bus 27 4 5 1 Round Robin Arbitration The MLB channel...

Page 804: ...uffer Start Address CNBCRn BSA defines the beginning address of the Next Buffer in system memory Buffer End Address CNBCRn BEA determines the end of the Next Buffer in system memory Buffer Current Add...

Page 805: ...fer as CNBCRn BEA is loaded into CCBCRn BFA See Note 1 in Figure 27 19 A Buffer Start interrupt is generated CSCRn STS 3 set which informs software that hardware has updated CCBCRn cleared the local c...

Page 806: ...trol packet that is broken or has an error CCBCRn BCA is reloaded with the start address of the last packet and the broken packet is overwritten This mechanism ensures that system software can always...

Page 807: ...Rn BCA Additionally the end of the Next Buffer becomes the end of the Current Buffer as CNBCRn BEA is loaded into CCBCRn BFA See Note 1 in Figure 27 20 A Buffer Start interrupt is generated CSCRn STS...

Page 808: ...ring Logical channels can be programmed to operate using circular buffering by programming CECRn MDS 1 0 01 It is recommended that circular buffering be used with synchronous channels only CECRn CT 1...

Page 809: ...buffer beginning and ending addresses are defined software must set the CSCRn RDY bit to initiate buffer processing At the start of buffer processing the beginning address of the circular buffer CNBCR...

Page 810: ...hronization feature for a synchronous logical channel by setting CECHRn FSE When enabled the synchronous logical channel begins transmitting and receiving data only at a MLB frame boundary When the lo...

Page 811: ...r Loop Back Test Mode operation software must perform the following steps Set the logical ChannelAddresses for Channel 0 and 1 They cannot be the same address Enable Channel 0 for receiving synchronou...

Page 812: ...Loop Figure 27 23 Main Loop MLB module System Reset InitDevice ReturnInitDevice no yes Lock Initialize MLB Module Hardware Channels n 0 MediaLB ChgChann ReturnChgChan InitChann ReturnInitChan n yes n...

Page 813: ...isable loop back test mode Select MediaLB clock speed Select MediaLB pin mode Set system endianness Set device address Set base address registers Write data to SMCR Write data to SBCR at PBI address 0...

Page 814: ...Rn CA 8 1 Write data to CECRn at PBI address 0x10 4 n Determine isochronous flow control mechanism CECRn FSE Determine isochronouspacket length CECRn IPL 7 0 For DMA Mode ping pong buffering the inter...

Page 815: ...ialize DMA Buffer InitDMABuffern ReturnDMABuffer Write data to CNBCRn at PBI address 0x13 4 n Determine next buffer start address CNBCRn 15 0 Determine next buffer end address CNBCRn 31 16 Set RDY to...

Page 816: ...annel Interrupt n num_of_chans ProcCintDMA ReturnCintDMA Read channel status from CSCRn at PBI address 0x11 4 n ProcessCint ReturnCint CLEAR INTERRUPTS Write CSCRn to 0x0000_FFFF at PBI address 0x11 4...

Page 817: ...memory Host bus error DMA current buffer done DMA current buffer started Break received on MediaLB during Current Buffer Protocol error detected on MediaLB during current buffer Disable channel and n...

Page 818: ...l Interrupt part 2 DMA current buffer done ProcCintDMA ReturnCintDMA Notify application Notify application Break request detected on MediaLB during previous buffer Protocol error detected on MediaLB d...

Page 819: ...Rn HBE Host bus error ProcCintDMACir ReturnCintDMACir Disable channel and notify application Buffer overflow for RX Buffer underflow for TX Protocol error detected on MediaLB during current buffer Bre...

Page 820: ...PBI address 0x02 Notify application CLEAR INTERRUPTS Write SDCR to 0x0000_001F SSCR SDR Detect system reset command Detect network lock Detect scan command Detect system subcommand ProcessSint ReturnF...

Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...

Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...

Page 823: ...ications needs while providing a consistent user interface with previous eMIOS implementations The PXN20 has one eMIOS200 module that implements 16 bit counters 28 1 1 Block Diagram Figure 28 1 shows...

Page 824: ...Counter Buses Time Bases Counter Buses Time Bases All Submodules Internal Counter Clock Enable IIB Output Disable Input 3 0 Global Time Base Enable Global Time Base Bit GTBE Output System Clock BIU IP...

Page 825: ...mode These modes are briefly described in this section Run mode is the normal operation mode and is described in Section 28 4 Functional Description Module disable mode is used for MCU power managemen...

Page 826: ...annel15 Channel8 Channel7 Channel13 Channel12 Channel11 Channel10 Counter_bus_C Channel Type A Channel Type B Channel Type C IP Bus Global Bus Interface Prescaler Clock Counter_bus_A eMIOS A PXN20 Cha...

Page 827: ...d I O functionality to be provided On the PXN21 19 of these channels are implemented on the device On the PXN20 12 of these channels are implemented Table 28 1 Supported Modes on PXN20 eMIOS Modules D...

Page 828: ...unified channel status and control register EMIOS_CSRn NOTE All eMIOS channels support both input and output functions When the eMIOS function is the primary function of a pin then both the input and...

Page 829: ...000 28 3 2 8 28 14 0x0030 EMIOS_CSR 0 Channel Status Register R 0x0000_0000 28 3 2 9 28 19 0x0034 EMIOS_ALTA 0 2 Alternate A Register R W 0x0000_0000 28 3 2 10 28 20 0x0038 0x003F Reserved Unified Cha...

Page 830: ...ble 28 4 Unified Channel Base Offsets Unified Channel Offset from EMIOS_BASE 0xFFFE_4000 Unified Channel Offset from EMIOS_BASE 0xFFFE_4000 Unified Channel 0 0x0020 Unified Channel 16 0x0220 Unified C...

Page 831: ...t the access to registers EMIOS_MCR EMIOS_OUDR and EMIOS_UCDIS 0 Clock is running 1 Enter low power mode FRZ Freeze Bit Enables the eMIOS200 to freeze the registers of the unified channels when debug...

Page 832: ...0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 4 eMIOS200 Global Flag Register EM...

Page 833: ...able transfers from registers A2 to A1 and B2 to B1 Each bit controls one channel 0 Transfer enabled Depending on the operation mode transfer may occur immediately or in the next period Unless stated...

Page 834: ...accesses for all operation modes For more information see section Section 28 4 1 1 Unified Channel Modes of Operation Depending on the channel configuration it may have EMIOS_CBDR register or not Thi...

Page 835: ...S_CBDR n Values Assignment Operation Mode Register Access Write Read Write Read Alternate Read GPIO A1 A2 A1 B1 B2 B1 SAIC1 A2 B2 B2 SAOC1 1 In these modes the register EMIOS_CBDR n is not used but B2...

Page 836: ...e 28 10 eMIOS200 Control Register EMIOS_CCR n Table 28 10 EMIOS_CCR n Field Descriptions Field Description FREN Freeze Enable Bit The FREN bit if set and validated by FRZ bit in EMIOS_MCR register fre...

Page 837: ...Prescaled clock 1 Main clock FEN FLAG Enable Bit The FEN bit allows the unified channel FLAG bit to generate an interrupt signal or a DMA request signal the type of signal to be generated is defined b...

Page 838: ...defined by the EDPOL bit 1 No FLAG is generated For SAOC mode the EDSEL bit selects the behavior of the output flip flop at each match 0 The EDPOL value is transferred to the output flip flop 1 The ou...

Page 839: ...111 Reserved 001_0000 MC Modulus Counter Up counter with clear on match start internal clock 001_0001 MC Modulus Counter Up counter with clear on match start external clock 001_0010 MC Modulus Counter...

Page 840: ...MCB Modulus Counter Up Down counter with flag on A1 match external clock 101_0110 MCB Modulus Counter Up Down counter with flag on A1 match or cycle boundary internal clock 101_0111 MCB Modulus Counte...

Page 841: ...hen the FLAG bit was already set This bit can be cleared by clearing the FLAG bit or by software writing a 1 0 Overrun has not occurred 1 Overrun has occurred OVFL Overflow Bit The OVFL bit indicates...

Page 842: ...reset 28 4 1 Unified Channel UC Figure 28 13 shows the unified channel block diagram Each unified channel consists of Counter bus selector which selects the time base to be used by the channel for all...

Page 843: ...fied channel control block diagram channel_controller ipd_done ipd_req uc_int_flag biu_channel_en n biu_a_en biu_b_en biu_cnt_en Clock Prescaler biu_control_en biu_status_en ips_byte 7 0 ips_byte 15 8...

Page 844: ...ut Output GPIO Mode In GPIO mode all input capture and output compare functions of the unified channel are disabled the internal counter EMIOS_CCNTR n register is cleared and disabled All control bits...

Page 845: ...ADR n returns the value of register A2 The channel is ready to capture events as soon as SAIC mode is entered coming out from GPIO mode The events are captured as soon as they occur thus reading regis...

Page 846: ...is entered coming out from GPIO mode the output flip flop is set to the complement of the EDPOL bit in the EMIOS_CCR n register Counter bus can be either internal or external and is selected through...

Page 847: ...this leading edge is detected the count value of the selected time base is latched into register B2 the FLAG bit is not set When the trailing edge is detected the count value of the selected time bas...

Page 848: ...updates when EMIOS_CADR n and EMIOS_CBDR n register reads occur The A1 register has always coherent data related to A2 register When EMIOS_CADR n read is performed the B1 register is loaded with the...

Page 849: ...registers B1 are meaningless On the second and subsequent captures the FLAG line is set and data in register B2 is transferred to register B1 When the second edge of the same polarity is detected the...

Page 850: ...nabled to occur at the transfer edges which is the leading edge in the Figure 28 23 example Figure 28 23 A1 and B1 Updates at EMIOS_CADR n and EMIOS_CBDR n Reads 0x000500 0x001000 0x001100 0x001250 0x...

Page 851: ...abled output compares occur on registers A1 and B1 pulses continue to be generated regardless of the state of the FLAG bit At any time the FORCMA and FORCMB bits allow the software to force the output...

Page 852: ...A1 Value1 B1 Value2 A2 A1 according to OU n bit B2 B1 according to OU n bit 0x000500 0x001000 0x001100 0x001000 0x001100 MODE 6 1 Selected Counter Bus 0x0 0x2 FLAG Set Event A1 Value2 0xx Output Flip...

Page 853: ...n continuous mode of operation the following steps should be performed assuming FLAG is initially cleared 1 Wait for FLAG assertion 2 Read EMIOS_CADR n register 3 Read EMIOS_CBDR n register 4 Clear FL...

Page 854: ...xxx 0x001500 0x000090 0x000090 0x007000 0x001500 0x007000 0x001000 FLAG Pin Register A1 Match 0x001500 Input Signal2 0x001000 A1 events A1 events no events events 0x000400 Notes 4 EMIOS_CADR n A2 when...

Page 855: ...measurements when reading EMIOS_CCNTR n after the FLAG is set the software must check if the time base value is out of the time interval defined by registers A1 and B1 Alternatively register A2 alway...

Page 856: ...d to the direction signal and UC n 1 input pin must be connected to the count signal of the quadrature encoder UC n EDPOL bit selects count direction according to direction signal and UC n 1 EDPOL bit...

Page 857: ...nt value until it matches the value in register A1 Register B1 is cleared and is not accessible to the MCU The MODE 4 bit selects up mode or up down mode when cleared or set respectively When in up co...

Page 858: ...set at the same time the counter is cleared See Figure 28 57 and Figure 28 61 Internal clock source is selected if MODE 6 is cleared In this case the internal counter clears when the match signal is a...

Page 859: ...DR n register MODE 6 bit selects the internal clock source if set to 0 or external if set to 1 When the external clock is selected the input channel pin is used as the channel clock source The active...

Page 860: ...od is defined by the expression 2 A1 2 Figure 28 35 shows the counter cycle for several A1 values Register A1 is loaded with A2 register value at the cycle boundary Any value written to A2 register wi...

Page 861: ...ounter Mode Figure 28 38 shows the A1 register update in up down counter mode Note that A2 can be written at any time within cycle n in order to be used in cycle n 1 Thus A1 receives this new value at...

Page 862: ...er To avoid this the user must start OPWFMB only if the value stored at internal counter is fewer than the value that EMIOS_CBDR register stores When a match on comparator A occurs the output register...

Page 863: ...h signal is used to trigger the output pin transition instead of the negedge used when A1 0x00_0001 A1 posedge match signal from cycle n 1 occurs at the same time as B1 negedge match signal from cycle...

Page 864: ...used to control the update of these registers thus allowing to delay the A1 and B1 registers update for synchronization purposes In Figure 28 41 it is assumed that the channel and global prescalers ar...

Page 865: ...is functionality targets applications that use active high signals and a high to low transition at A1 match In this case EDPOL should be set to 0 Cycle n Cycle n 1 Cycle n 2 A1 Value B1 Value B2 Value...

Page 866: ...he level corresponding to a match on comparators A or B respectively Similar to a B1 match FORCMB sets the internal counter to 0x00_0001 The FLAG bit is not set by the FORCMA or FORCMB bits being asse...

Page 867: ...ntains the ideal duty cycle for the PWM signal and is compared with the selected time base Register B1 contains the dead time value and is compared against the internal counter For a leading edge dead...

Page 868: ...flop is set to the value of the EDPOL bit In the following match between register A1 and the selected time base the output flip flop is set to the complement of the EDPOL bit This sequence repeats con...

Page 869: ...gister A1 and the selected time base the internal counter is set to 0x00_0001 and B1 matches are enabled When the match between register B1 and the selected time base occurs the output flip flop is se...

Page 870: ...ime insertion mode lead or trail In lead dead time insertion FORCMA force a transition in the output flip flop to the opposite of EDPOL In trail dead time insertion the output flip flop is forced to t...

Page 871: ...is set to one and OPWMCB mode with trail dead time insertion 100 duty cycle signals can be generated if B1 occurs at or after the cycle boundary external counter 1 Only values different than 0x00_000...

Page 872: ...to Figure 28 39 which shows the delay from matches to output flip flop transition in OPWFMB mode The operation of OPWMCB mode is similar to OPWFMB regarding matches and output pin transition 28 4 1 1...

Page 873: ...ch from cycle n has precedence over B1 match from cycle n 1 A1 matches are masked out if they occur after B1 match within the same cycle Any value written to A2 or B2 on cycle n is loaded to A1 and B1...

Page 874: ...ignal Figure 28 49 OPWMB Mode with 0 Duty Cycle Figure 28 50 shows the operation of the OPWMB mode with the output disable signal asserted The output disable forces a transition in the output pin to t...

Page 875: ...ted 28 4 1 1 15 Output Pulse Width Modulation with Trigger OPWMT Mode OPWMT mode MODE 0 6 010_0110 is intended to support the generation of Pulse Width Modulation signals where the period is not modif...

Page 876: ...CBDR n address gives access to B2 register for write and B1 register for read Register B1 defines the trailing edge of the PWM output pulse and as such the duty cycle of the PWM signal To synchronize...

Page 877: ...B assertion If subsequent matches occur on comparators A1 and B the PWM pulses continue to be generated regardless of the state of the FLAG bit At OPWMT mode entry the output flip flop is set to the c...

Page 878: ...Output Flip Flop A1 Value1 write to B2 0x000400 B1 Value B2 Value2 0x000700 Match B1 write to A1 0xxxxxxx 0x000400 0x001000 0x000700 and B2 0x001000 Match A1 Match B1 Match A1 Notes 1 EMIOS_CADR n A1...

Page 879: ...ting If a counter overflow occurs the new pin value is validated In this case it is transmitted as a pulse edge to the edge detector If the opposite edge appears on the pin before validation overflow...

Page 880: ...desired value for prescaling rate at UCPRE bits in EMIOS_CCR n register 3 Enable channel prescaler by writing 1 at UCPREN bit in EMIOS_CCR n register 4 Enable global prescaler by writing 1 at GPREN bi...

Page 881: ...ing is enabled by setting the GPREN bit in the EMIOS_MCR The counter can be stopped at any time by clearing this bit thereby stopping the internal counter in all the unified channels 28 4 3 1 Effect o...

Page 882: ...he update of these output signals In order to guarantee the internal counters of correlated channels are incremented in the same clock cycle the internal prescalers must be set before enabling the glo...

Page 883: ...nal Counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Match Value 3 Clock See Note PRESCALED CLOCK RATIO 1 Bypassed When a match occurs the first clock cycle is used to clear the internal counter...

Page 884: ...ion Reading the EMIOS_CADR n register again in the same period of the last read of EMIOS_CBDR n register may lead to incoherent results This occurs if the last read of EMIOS_CBDR n register occurred a...

Page 885: ...mented on the PXN21 The CAN protocol interface CPI sub module manages the serial communication on the CAN bus requesting RAM access for receiving and transmitting message frames validating received me...

Page 886: ...ro to eight bytes data length Programmable bit rate as high as 1 Mbit s Content related addressing 64 flexible message buffers MBs of 0 to 8 bytes data length Each message buffer configurable as Rx or...

Page 887: ...priority on individual Tx message buffers Hardware cancellation on Tx message buffers Time stamp based on 16 bit free running timer Global network time synchronized by a specific message Maskable inte...

Page 888: ...t and receive interrupts are generated 29 1 3 5 Module Disabled Mode This low power mode is entered when the MDIS bit in the CANx_MCR register is asserted When disabled the clocks to the CAN protocol...

Page 889: ...10 CANx_RXGMASK Rx Global Mask R W 0xFFFF_FFFF 29 3 4 4 1 29 18 0x0014 CANx_RX14MASK Rx Buffer 14 Mask R W 0xFFFF_FFFF 29 3 4 4 2 29 19 0x0018 CANx_RX15MASK Rx Buffer 15 Mask R W 0xFFFF_FFFF 29 3 4 4...

Page 890: ...as shown below Rx MB ID bits 3 31 of ID word corresponding to message ID bits 0 28 RXIDA bits 2 30 of ID Table corresponding to message ID bits 0 28 Note that the mask bits one to one correspondence o...

Page 891: ...is represented in Figure 29 2 Both extended and standard frames 29 bit identifier and 11 bit identifier respectively used in the CAN specification version 2 0 Part B are represented 0 1 2 3 4 5 6 7 8...

Page 892: ...d appears on the CAN bus PRIO Local Priority This 3 bit field is only used when LPRIO_EN bit is set in CANx_MCR and it only makes sense for Tx buffers These bits are not transmitted They are appended...

Page 893: ...iption X 1000 INACTIVE MB does not participate in the arbitration process X 1001 ABORT MB was configured as Tx and CPU aborted the transmission This code is only valid when AEN bit in CANx_MCR is asse...

Page 894: ...t See Section 29 4 6 Rx FIFO for more information 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x80 SRR IDE RTR LENGTH TIME STAMP 0x84 ID Extended Standard ID...

Page 895: ...ejected RXIDA Rx Frame Identifier Format A Specifies an ID to be used as acceptance criteria for the FIFO In the standard frame format only the 11 most significant bits 3 to 13 are used for frame iden...

Page 896: ...bled or not When FEN is set MBs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region 0x80 0xFF is used by the FIFO engine See Section 29 3 3 Rx FIFO Stru...

Page 897: ...eze mode request is negated then this bit is negated once the FlexCAN prescaler is running again If freeze mode is requested while FlexCAN is disabled then the FRZ_ACK bit is only set when the low pow...

Page 898: ...ovided for backwards compatibility reasons It controls whether the local priority feature is enabled or not It is used to extend the ID used during the arbitration process With this extended ID concep...

Page 899: ...uency is equal to the CPI clock frequency The maximum value of this register is 0xFF that gives a minimum SCK frequency equal to the CPI clock frequency divided by 256 For more information refer to Se...

Page 900: ...covers from bus off state If this bit is negated automatic recovering from bus off state occurs according to the CAN Specification 2 0B If this bit is set automatic recovering from bus off is disabled...

Page 901: ...transparent to the user except for the fact that the data takes some time to be actually written to the register If desired software can poll the register to discover when the data was actually writte...

Page 902: ...n the FEN bit in CANx_MCR is set FIFO enabled the Table 29 9 Mask Examples for Standard Extended Message Buffers Base ID ID28 ID18 IDE Extended ID ID17 ID0 Match MB2 ID 1 1 1 1 1 1 1 1 0 0 0 0 MB3 ID...

Page 903: ...he PXN20 setting the BCC bit in CANx_MCR causes the CANx_RX15MASK register to have no effect on the module operation When the BCC bit is negated CANx_RX15MASK is used as acceptance mask for the Identi...

Page 904: ...FlexCAN state is error passive and either TXECTR or RXECTR decrements to a value less than or equal to 127 while the other already satisfies this condition the FLT_CONF field in the CANx_ESR is update...

Page 905: ...T0_ERR ACK_ERR CRC_ERR FRM_ERR and STF_ERR therefore these bits must not be read speculatively Offset Base 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0...

Page 906: ...nding a passive error flag that detects dominant bits BIT0_ERR Bit 0 Error Indicates when an inconsistency occurs between the transmitted and the received message in a bit A read clears BIT0_ERR 0 No...

Page 907: ...ted by soft reset the FLT_ CONF field is not affected by soft reset if the LOM bit is asserted 00 Error active 01 Error passive 1n Bus off BOFF_INT Bus Off Interrupt This status bit is set when FlexCA...

Page 908: ...2 Field Descriptions Field Description BUFnM Message Buffer n Mask Enables or disables the respective FlexCAN message buffer MB63 to MB32 Interrupt 0 The corresponding buffer Interrupt is disabled 1 T...

Page 909: ...2 13 14 15 R BUF 63I BUF 62I BUF 61I BUF 60I BUF 59I BUF 58I BUF 57I BUF 56I BUF 55I BUF 54I BUF 53I BUF 52I BUF 51I BUF 50I BUF 49I BUF 48I W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 2...

Page 910: ...h bit represents the respective FlexCAN message buffer MB31 to MB8 interrupt Write 1 to clear 0 No such occurrence 1 The corresponding buffer has successfully completed transmission or reception BUF7I...

Page 911: ...y bits or the MB ordering Before proceeding with the functional description an important concept must be explained A message buffer is said to be active at a given time if it can participate in the ma...

Page 912: ...CPU is not able to update it until the interrupt flag be negated by CPU It means that the CPU must clear the corresponding CANx_IFLAG before starting to prepare this MB for a new transmission or recep...

Page 913: ...e 1000 to the code field to inactivate the MB but then the pending frame may be transmitted without notification see Section 29 4 5 2 Message Buffer Deactivation If the MB already programmed as a rece...

Page 914: ...nterrupt signal is generated due to the frame reception To be able to receive CAN frames through the FIFO the CPU must enable and configure the FIFO during freeze mode see Section 29 4 6 Rx FIFO Upon...

Page 915: ...implement a reception queue in addition to the full featured FIFO to allow more time for the CPU to service the MBs By programming more than one MB with the same ID received messages are queued into...

Page 916: ...written into the code field the interrupt flag is set in the CANx_IFLAG and an interrupt is optionally generated to the CPU If the CPU writes the abort code before the transmission begins internally...

Page 917: ...ion of a Tx MB causes it not to be transmitted end of move out After this point it is transmitted but no interrupt is issued and the code field is not updated In order to avoid this situation the abor...

Page 918: ...agement of read and write pointers is done internally by the FIFO engine The CPU can read the received frames sequentially in the order they were received by repeatedly accessing a Message Buffer stru...

Page 919: ...ot used in remote frame matching and all ID bits except RTR of the incoming received frame should match In the case that a remote request frame was received and matched a MB this message buffer immedi...

Page 920: ...ose the CAN waveform A time quantum is the atomic unit of time handled by FlexCAN A bit time is subdivided into three segments1 reference Figure 29 16 and Table 29 17 SYNCSEG This segment has a fixed...

Page 921: ...ent Syntax Syntax Description SYNCSEG System expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point Sample...

Page 922: ...and the CAN bit rate Figure 29 17 Arbitration Match and Move Time Windows 29 4 8 Modes of Operation Details 29 4 8 1 Freeze Mode This mode is entered by asserting the HALT bit in the CANx_MCR or when...

Page 923: ...ts Tx pin as recessive Shuts down the clocks to the CPI and MBM sub modules Sets the NOT_RDY and LPM_ACK bits in CANx_MCR The bus interface unit continues to operate enabling the CPU to access memory...

Page 924: ...ce from 0x0060 to 0x007F is reserved for SMB usage and the space from 0x0080 to 0x008F is used by the one MB This leaves us with the available space from 0x0090 to 0x047F The available memory in the m...

Page 925: ..._EN bit If required disable frame self reception by setting the SRX_DIS bit Enable the FIFO by setting the FEN bit Enable the abort mechanism by setting the AEN bit Enable the local priority feature b...

Page 926: ...Controller Area Network FlexCAN PXN20 Microcontroller Reference Manual Rev 1 29 42 Freescale Semiconductor...

Page 927: ...PI operates as a basic SPI or as a queued SPI through the use of internal FIFOs Deserial serial interface DSI configuration where the DSPI serializes the parallel input signals and deserializes receiv...

Page 928: ...transmit operation using the TX FIFO with depth of 4 entries Buffered receive operation using the RX FIFO with depth of 4 entries TX and RX FIFOs can be disabled individually for low latency updates t...

Page 929: ...to transmit with an empty Transmit FIFO TFUF RX FIFO is not empty RFDF Frame received while Receive FIFO is full RFOF Modified SPI transfer formats for communication with slower peripheral devices Mod...

Page 930: ...on the frame boundaries In this configuration SPI data transmission has higher priority than DSI data transmission 30 1 4 Modes of Operation The DSPI has five modes of operation that can be divided i...

Page 931: ...ic mode and configuration of the DSPI 30 2 External Signal Description The DSPI supports the following external signals Refer to Table 3 1 and Section 3 4 Detailed Signal Description for detailed sign...

Page 932: ...I_SR DSPI status register R 0x0000_0000 30 3 2 4 30 16 0x0030 DSPI_RSER DSPI DMA interrupt request select and enable register R W 0x0000_0000 30 3 2 5 30 18 FIFO Registers 0x0034 DSPI_PUSHR DSPI push...

Page 933: ...13 14 15 R MSTR CONT_ SCKE DCONF FRZ MTFE PCS SE ROOE 0 0 PCS IS5 PCS IS4 PCS IS3 PCS IS2 PCS IS1 PCS IS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 M...

Page 934: ...is full and new data is received the data from the transfer that generated the overflow is either ignored or shifted in to the shift register If the ROOE bit is asserted the incoming data is shifted i...

Page 935: ...Counter The CLR_TXF bit is always read as zero 0 Do not clear the TX FIFO Counter 1 Clear the TX FIFO Counter CLR_RXF Clear RX FIFO CLR_RXF is used to flush the RX FIFO Writing a 1 to CLR_RXF clears...

Page 936: ...e Section 30 3 2 10 DSPI DSI Configuration Register DSPI_DSICR When the DSPI is configured as a DSI bus slave the DSPI_CTAR1 register is used In CSI configuration the transfer attributes are selected...

Page 937: ...he overall baud rate is divide by two or divide by three of the system clock then neither the continuous SCK enable or the modified timing format enable bits should be set 0 The baud rate is computed...

Page 938: ...sertion of PCS and the first edge of the SCK This field is only used in master mode The table below lists the prescaler values See the CSSCK 0 3 field description for details on how to compute the PCS...

Page 939: ...clock period and it is computed according to the following equation Eqn 30 2 See Section 30 4 7 3 After SCK Delay tASC for more details DT Delay after Transfer Scaler The DT field selects the delay af...

Page 940: ...40 1 1 11 57 43 Table 30 7 DSPI Transfer Frame Size FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 9 0001 Reserved 1001 10 0010 Reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7...

Page 941: ...10 128 1110 32768 0111 256 1111 65536 Table 30 10 DSPI Delay after Transfer Scaler DT Delay after Transfer Scaler Value DT Delay after Transfer Scaler Value 0000 2 1000 512 0001 4 1001 1024 0010 8 101...

Page 942: ...rames in Continuous Peripheral Chip Select mode DSPIx_PUSHR CONT 1 and when changing DSPIx_CTARn bit fields between frames adhere to the following conditions as they can generate error if If DSPIx_CTA...

Page 943: ...FIFO The TFFF bit is set while the TX FIFO is not full The TFFF bit can be cleared by host software or an acknowledgement from the DMA controller when the TX FIFO is full 0 TX FIFO is full 1 TX FIFO...

Page 944: ...nable The TCF_RE bit enables TCF flag in the DSPI_SR to generate an interrupt request 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled EOQF_ RE DSPI Finished Request Enable T...

Page 945: ...hat the data with reset CONT bit is written to DSPI_PUSHR register before previous data sub frame with CONT bit set transfer is over RFOF_RE Receive FIFO Overflow Request Enable The RFOF_RE bit enable...

Page 946: ...Chip Select signals to their inactive state between transfers 1 Keep Peripheral Chip Select signals asserted between transfers CTAS Clock and Transfer Attributes Select The CTAS field selects which DS...

Page 947: ...he DSPI_TXFRn registers does not alter the state of the TX FIFO PCSn Peripheral Chip Select 0 7 The PCS bits select which PCS signals are asserted for the transfer 0 Negate the PCS x signal 1 Assert t...

Page 948: ...PI_TXFR0 0x0040 DSPI_TXFR1 0x0044 DSPI_TXFR2 0x0048 DSPI_TXFR3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TXCMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R T...

Page 949: ...0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 11 DSPI Receive FIFO Registers 0 15 DSPI_R...

Page 950: ...alization is initiated when the current DSI data differs from the previous DSI data shifted out The DSPI_COMPR register is compared with the DSPI_SDR or DSPI_ASDR register to detect a change in data R...

Page 951: ...re only used when TSB is enabled For non TSB configurations only the least 16 significant bits are used Offset DSPI_BASE 00C0 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SER_DATA W Reset 0 0 0...

Page 952: ...The DSPI_DDR register holds the signal states for the parallel output signals The DSPI_DDR is read only and it is memory mapped so that host software can read the incoming DSI frames Table 30 20 DSPI...

Page 953: ...Deserialization Data Register DSPI_DDR Table 30 22 DSPI_DDR Field Description Field Description DESER_DATA Deserialized Data When TSB configuration is set the DESER_DATA field holds deserialized data...

Page 954: ...pe of data transferred whether DSI or SPI dictates which CTAR the CSI configuration uses See Section 30 3 2 3 DSPI Clock and Transfer Attributes Registers 0 7 DSPI_CTARn for information on DSPI_CTARn...

Page 955: ...Section 30 4 13 Power Saving Features for information on the power saving features of the DSPI 30 4 1 Modes of Operation The DSPI modules have the following modes available Master mode Slave mode Modu...

Page 956: ...PI operates as bus slave when the MSTR bit in the DSPI_MCR register is negated The DSPI slave is selected by a bus master by having the slave s SS asserted In slave mode the SCK is provided by the bus...

Page 957: ...uration registers of the DSPI without causing undetermined results The TXRXS bit in the DSPI_SR is negated in this state In the running state serial transfers take place The TXRXS bit in the DSPI_SR i...

Page 958: ...The FIFO operations are similar for the master mode and slave mode The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command fi...

Page 959: ...ons as a buffer of SPI data and SPI commands for transmission The TX FIFO holds four entries each consisting of a command field and a data field SPI commands and data are added to the TX FIFO by writi...

Page 960: ...g the DSPI POP RX FIFO Register DSPI_POPR RX FIFO entries can only be removed from the RX FIFO by reading the DSPI_POPR or by flushing the RX FIFO For more information on the DSPI_POPR refer to Sectio...

Page 961: ...egister The various features of the DSI configuration are set in the DSPI_DSICR For more information on the DSPI_DSICR refer to Section 30 3 2 10 DSPI DSI Configuration Register DSPI_DSICR The DSPI is...

Page 962: ...30 21 DSI Serialization Diagram 30 4 4 4 DSI Deserialization When all bits in a DSI frame have been shifted in the frame is copied to the DSPI DSI Deserialization Data Register DSPI_DDR This register...

Page 963: ...30 4 4 5 2 Change In Data Control For change in data control a transfer is initiated when the data to be serialized has changed since the transfer of the last DSI frame A copy of the previously trans...

Page 964: ...select signals indicate whether DSI data or SPI data is transmitted The user must configure the DSPI so that the two CTAR registers associated with DSI data and SPI data assert different peripheral c...

Page 965: ...cts the source of the serialized data and asserts the appropriate chip select signal 30 4 5 2 CSI Deserialization The deserialized frames in CSI configuration go into the DSPI_SDR or the RX FIFO based...

Page 966: ...SPI Data transfers between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software See Figure 30 26 for conceptual diagram of the queue data tran...

Page 967: ...30 6 Table 30 27 shows an example of the computed PCS to SCK delay 30 4 7 3 After SCK Delay tASC The after SCK delay is the length of time between the last edge of SCK and the negation of PCS See Figu...

Page 968: ...y is configurable as outlined in the DSPI_CTARn registers When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period When in TSB and continuous mode the delay is programme...

Page 969: ...timing of the PCSS signal relative to PCS signals Figure 30 28 Peripheral Chip Select Strobe Timing Table 30 30 Delay after Transfer Computation Example in TSB Configuration PDT field Tdt1 Tsck 1 Som...

Page 970: ...and sampling of the data on the SIN and SOUT pins The PCS signals serve as enable signals for the slave devices When the DSPI is the bus master the CPOL and CPHA bits in the DSPI clock and transfer a...

Page 971: ...ts are described in Section 30 4 8 1 Classic SPI Transfer Format CPHA 0 and Section 30 4 8 2 Classic SPI Transfer Format CPHA 1 The Modified Transfer Formats are described in Section 30 4 8 3 Modified...

Page 972: ...For the CPHA 0 condition of the master TCF and EOQF are set and the RXCTR counter is updated at the next to last serial clock edge of the frame edge 15 of Figure 30 29 For the CPHA 0 condition of the...

Page 973: ...CTR counters are updated on the same clock edge 30 4 8 3 Modified SPI DSI Transfer Format MTFE 1 CPHA 0 In this modified transfer format both the master and the slave sample later in the SCK period th...

Page 974: ...with a lighter shaded arrow Figure 30 31 DSPI Modified Transfer Format MTFE 1 CPHA 0 Fsck Fsys 4 30 4 8 4 Modified SPI DSI Transfer Format MTFE 1 CPHA 1 Figure 30 32 shows the modified transfer format...

Page 975: ...Rn CPHA 1 if the After SCK delay scaler ASC time is set to less than 1 2 SCK clock period the DSPI may not complete the transaction the TCF flag will not be set serial data will not received and last...

Page 976: ...PCS signal for the next transfer is the same as for the current transfer the PCS signal remains asserted for the duration of the two transfers The delay between transfers tDT is not inserted between...

Page 977: ...peripherals that require a continuous clock Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPI_MCR Continuous SCK is valid in all configurations Continuous SCK is only supported for C...

Page 978: ...ous SCK disables the PCS to SCK delay and the after SCK delay The delay after transfer is fixed at one SCK cycle Figure 30 36 shows timing diagram for continuous SCK format with continuous selection d...

Page 979: ...Channel MSC feature to be performed In the TSB configuration the DSPI can send from 4 to as many as 32 data bits The source of these bits can be either the DSPI DSI Alternate Serialization Data Regis...

Page 980: ...0 1 PCS Switch Over Timing When in TSB mode it is possible to switch the set of PCS signals that are driven during the first part of the frame to a different set of PCS signals during the second part...

Page 981: ...s defined as TSCK The length of the command frame passive phase TDT should always be fixed to a minimum of 1x TSCK 30 4 10 3 TSB Data Frame Format A data frame is transmitted from the TSB controller t...

Page 982: ...demultiplexer decoder can be connected to the DSPI Figure 30 42 DSPI PCS Expansion and Deglitching 30 4 12 DMA and Interrupt Conditions The DSPI has six conditions that can generate interrupt request...

Page 983: ...e DSPI_RSER selects whether a DMA request or an interrupt request is generated 30 4 12 3 Transfer Complete Interrupt Request TCF The transfer complete request indicates the end of the transfer of a se...

Page 984: ...ts three power saving strategies Halt mode Module disable mode clock gating of non memory mapped logic Clock gating of slave interface signals and clock to memory mapped logic 30 4 13 1 Halt Mode By s...

Page 985: ...tion 30 5 1 How to Change Queues DSPI queues are not part of the DSPI module but the DSPI includes features in support of queue management Queues are primarily supported in SPI configuration This sect...

Page 986: ...is clear 30 5 3 Delay Settings Table 30 36 shows the values for the Delay after Transfer TDT and CS to SCK Delay TCSC that can be generated based on the prescaler values and the scaler values set in t...

Page 987: ...m clock For other system clock frequencies the customer can recompute the values using Section 30 5 3 Delay Settings For BITSE 0 8 bits per transfer For DT 0 0 425 s delay For this value the closest v...

Page 988: ...e concepts carry over to the RX FIFO See Section 30 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 30 4 3 5 Receive First In First Out RX FIFO Buffering Mechanism for detail...

Page 989: ...ter TX FIFO depth transmit FIFO depth 30 5 5 2 Address Calculation for the First in Entry and Last in Entry in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the fo...

Page 990: ...Deserial Serial Peripheral Interface DSPI PXN20 Microcontroller Reference Manual Rev 1 30 64 Freescale Semiconductor...

Page 991: ...agram of the eSCI illustrates the functionality and interdependence of major blocks see Figure 31 1 Figure 31 1 eSCI Block Diagram 31 1 2 Features The eSCI has these major features Full duplex operati...

Page 992: ...nsmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection 1 16 bit time noise detection 2 channel...

Page 993: ...nd Section 31 1 3 4 3 Entering Halt Mode from LIN Mode If the eSCI module is in halt mode and the system stop signal is de asserted and the LIN bit and the MDIS bit are 0 the eSCI module enters the SC...

Page 994: ...serted while a LIN byte field or character reception is running the eSCI module aborts the reception immediately None of the receiver related register flags will be set If the eSCI module is in LIN mo...

Page 995: ...0xC3FA_4000 eSCI_L 0xC3FA_8000 eSCI_M 0xC3FA_C000 Register Access Reset Value Section Page 0x0000 eSCI_BRR eSCI baud rate register R W 0x0004 31 3 2 1 31 6 0x0002 eSCI_CR1 eSCI control register 1 R W...

Page 996: ...of all zeroes into the upper byte A word write access to this register updates both the lower and upper byte immediately and is the recommended write access type for this register 31 3 2 2 eSCI Contr...

Page 997: ...s the parity bit generation and checking The location of the parity bits is shown in Section 31 4 2 Frame Formats 0 Parity bit generation and checking disabled 1 Parity bit generation and checking ena...

Page 998: ...ake up mode Note This bit should be set in SCI mode only SBK Send Break Character This bit controls the transmission of break characters which is described in Section 31 4 5 2 7 Break Character Transm...

Page 999: ...generation 0 BERR interrupt request generation disabled 1 BERR interrupt request generation enabled RXDMA Receive DMA Control This bit enables the receive DMA feature 0 Receive DMA disabled 1 Receive...

Page 1000: ...ated bit position in the SCI Data Register eSCI_SDR 0 The received parity bit is presented in the bit position related to the parity bit 1 The value 0 is presented in the bit position related to the p...

Page 1001: ...eception of the frame presented in SCI Data Register eSCI_SDR In case of an overrun error for subsequent frames this bit is set too 0 None of the selected errors occured 1 At least one of the selected...

Page 1002: ...CI mode only OR Overrun Flag This flag is set when an overrun was detected as described in Section 31 4 5 3 11 Receiver Overrun Note This flag is set in SCI mode only NF Noise Interrupt Flag This flag...

Page 1003: ...eup character is received as described in Section 31 4 6 6 LIN Wakeup STO Slave Timeout Interrupt Flag This interrupt flag is set when a Slave Not Responding Error is detected A detailed description i...

Page 1004: ...on disabled 1 RXRDY interrupt request generation enabled TXIE Transmit Data Ready Interrupt Enable This bit controls the eSCI_IFSR2 TXRDY interrupt request generation 0 TXRDY interrupt request generat...

Page 1005: ...LIN RX Frame Generation applies Figure 31 11 The initiation and transmit of a RX frame is described in Section 31 4 6 4 LIN RX Frame Generation Each write access to this register increments the intern...

Page 1006: ...in Section 31 4 6 4 LIN RX Frame Generation NOTE When the eSCI module is in LIN mode and transmits or receives a LIN frame if the CPU requests Stop Mode and the Stop Mode is left a subsequent triggere...

Page 1007: ...n and checking of checksum byte CRC CRC Enable This bit controls the generation of checking standard or enhanced LIN frames which are described in Section 31 4 6 2 LIN Frame Formats 0 Standard LIN fra...

Page 1008: ...x10 x8 x7 x4 x3 1 the polynomial used for the CAN protocol Offset ESCI_BASE 0x001A Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 SYNM EROE ERFE ERPE M2 0 0 0 0 0 0 0 0 W Reset...

Page 1009: ...ity error detection 1 eSCI_SDR ERR flag is set on parity error detection for the data provided in eSCI_SDR M2 Frame Format Mode 2 Together with the M bit of the Control Register 1 eSCI_CR1 this bit co...

Page 1010: ...and idle characters 31 4 2 1 Data Frame Formats Each data frame contains a character that is surrounded by a start bit an optional parity or address bit and one or two stop bits The supported data fr...

Page 1011: ...rmats 2 Stop Bits Table 31 16 Supported Data Frame Formats for RX only Control Frame Content eSCI_CR3 eSCI_CR1 Start Bits Payload Bits Stop Bits M2 M PE WAKE Character Bits Address Bits Parity Bits SC...

Page 1012: ...structure and content of the LIN break symbols is shown in Figure 31 20 Figure 31 20 LIN Break Symbol Format The structure and content of the SCI break characters is shown in Figure 31 21 Table 31 17...

Page 1013: ...CI_BRR determines the module clock divisor The baud rate clock is synchronized with the bus clock and drives the receiver The baud rate clock divided by 16 drives the transmitter The receiver has an a...

Page 1014: ...d rate generator is controlled by the value of the SBR 12 0 field in the eSCI Baud Rate Register eSCI_BRR The frequency of the transmitter clock is determined by Equation 31 1 and defines the length o...

Page 1015: ...zero 31 4 4 1 Faster Receiver Tolerance In this case the receiver has a higher baud rate than the transmitter thus the stop bit sampling starts already in the last transmitted payload bit To ensure t...

Page 1016: ...be calculated with the assumption that RS11 is sampled in the transmitted start bit and RS10 is sampled in the last stop bit For an frame with n payload bits and s stop bits the transmitter starts th...

Page 1017: ...frame format eSCI Control Register 1 eSCI_CR1 M eSCI Control Register 1 eSCI_CR1 PE eSCI Control Register 1 eSCI_CR1 WAKE eSCI Control Register 3 eSCI_CR3 M2 select parity type eSCI Control Register...

Page 1018: ...are triggered when the described condition or event occurs The send break bit SBK in the eSCI Control Register 1 eSCI_CR1 is checked for the start condition The internal commit bit iCMT the transmitt...

Page 1019: ...ith a start bit and appended with the parity bit if configured and the configured number of stop bits When the last stop bit has been transmitted and the application has not disabled the transmitter t...

Page 1020: ...module to enter this mode by setting the TXDMA bit in the eSCI Control Register 2 eSCI_CR2 From this point in time the module starts the generation of DMA requests and frame transmission Before enteri...

Page 1021: ...mitter while the preamble is transmitted and if the stop bit has been transmitted the transmitter goes into the idle state via the halt transition The transfer complete flag TC in the eSCI Interrupt F...

Page 1022: ...smitter is shown in Figure 31 27 Figure 31 27 Receiver State Diagram The current state of the receiver can be determined by the RE and RWU bit in the eSCI Control Register 1 eSCI_CR1 and the RACT stat...

Page 1023: ...e mode the RXD pin is disconnected from the eSCI module and the TXD pin is used for both receiving and transmitting Table 31 27 Receiver Application Transition Transition Command Condition Action Desc...

Page 1024: ...ampling described in Section 31 4 5 3 13 Bit Sampling During the reception the received bits are shifted into the internal shift register 31 4 5 3 7 Break Character Detection The receiver does not pro...

Page 1025: ...abled the receiver by clearing the receiver enable bit RE in the eSCI Interrupt Flag and Status Register 1 eSCI_IFSR1 the current frame is discarded and no flags are updated 31 4 5 3 10 DMA Controlled...

Page 1026: ...mark wake up mode is selected and the received frame has the address bit set the receive data register full flag RDRF in eSCI Interrupt Flag and Status Register 1 eSCI_IFSR1 is set If the receive inte...

Page 1027: ...st for baud rate mismatch the cyclic sample counter RSC is re synchronized by reset after successful start bit qualification A start bit is successfully qualified if no reception is ongoing and three...

Page 1028: ...bit and to detect noise a two out of three majority voting is performed on the samples RS8 RS9 and RS10 Table 31 31 summarizes the results of the data bit sample The receiver detects the number of da...

Page 1029: ...The data bit N 1 is sampled as 1 and 2 the data bit N is sampled as 0 and 3 a falling edge consisting of three consecutive 1 samples and a following 0 sample is detected and 4 the 0 sample of the fal...

Page 1030: ...1 35 Data Bit Synchronization Left Shifted Edges If the 0 sample of the falling edge condition is received at sample 9 or 10 no sample counter synchronization is performed 31 4 5 3 18 Stop Bit Verific...

Page 1031: ...Section 31 4 5 3 13 Bit Sampling the FE flag is set If the receiver has not detected an overrun and has detected a parity error as described in Section 31 4 5 3 19 Parity Checking the PF flag is set...

Page 1032: ...rk Wakeup Format 31 4 6 LIN Mode The eSCI provides support for the LIN protocol It can be used to automate most tasks of a LIN master In conjunction with the DMA interface it is possible to transmit e...

Page 1033: ...ame Formats The eSCI module allows to generate LIN frames for LIN slaves of LIN standards 1 3 and 2 0 31 4 6 2 1 Standard LIN Frames A standard LIN frame shown in Figure 31 38 consists of a break char...

Page 1034: ...pt flag before writing data into the eSCI LIN Transmit Register eSCI_LTR because the eSCI module sets the TXRDY one clock cycle after the write access The first data written to the eSCI LIN Transmit R...

Page 1035: ...for transmission the module generates the transmit DMA request and the DMA controller delivers the required data The application requests the eSCI module to enter this mode by setting the TXDMA bit i...

Page 1036: ...des the Identifier and Identifier Parity fields The second data written defines the number of data bytes requested from the LIN slave The third data written defines the CRC and checksum generation The...

Page 1037: ...e generation and reception The content of the header fields in the memory is the same as described in eSCI LIN Transmit Register eSCI_LTR LIN RX frame generation The TX DMA channel is used the fetch t...

Page 1038: ...ster must be read before normal operations can proceed 31 4 6 5 3 Standard Bit Error Detection The standard bit error detection is performed on each byte field transmission During the transmission of...

Page 1039: ...or is defined in LIN Specification Package Revision 1 3 December 12 2002 6 ERROR AND EXCEPTION HANDLING The LIN specification requires that a NO_RESPONSE_ERROR has to be detected if a message frame is...

Page 1040: ...he eSCI LIN Receive Register eSCI_LRR is not changed The data received most recently are lost 31 4 6 6 LIN Wakeup The section describes the LIN wakeup behavior of the eSCI module 31 4 6 6 1 LIN Wakeup...

Page 1041: ...n might incorrectly signal the occurrence of bit errors ESCI_IFSR1 BERR and frame error ESCI_IFSR1 FE and the transmitted frame might be incorrect 31 4 6 7 LIN Protocol Engine Reset The LIN protocol e...

Page 1042: ...eared 3 Clear and subsequently set the TE bit in the eSCI Control Register 1 eSCI_CR1 This set the internal iPRE bit which requests the preamble transmission 4 Write to the eSCI SCI Data Register eSCI...

Page 1043: ...cation Interface eSCI PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 31 53 The priority scheme of the transmitter described in Table 31 25 ensures that the preamble is transmitte...

Page 1044: ...Enhanced Serial Communication Interface eSCI PXN20 Microcontroller Reference Manual Rev 1 31 54 Freescale Semiconductor...

Page 1045: ...devices It also provides flexibility allowing additional devices to be connected to the bus for further expansion and system development The interface is designed to operate as fast as 100 kbps with...

Page 1046: ...l support from the CPU DMA mode is enabled by setting the DMAEN bit in the I2 C Bus Control Register IBCR DMA requests can be performed on all four I2 C channels The DMA interface is only valid when t...

Page 1047: ...ammable for one of 256 serial clock frequencies Software selectable acknowledge bit Interrupt driven byte by byte data transfer Arbitration lost interrupt with automatic mode switching from master to...

Page 1048: ...ed signal descriptions 32 3 Memory Map and Registers This section provides a detailed description of all I2 C registers 32 3 1 Module Memory Map Table 32 1 shows the I2 C memory map The address of eac...

Page 1049: ...is not the address sent on the bus during the address transfer 32 3 2 2 I2 C Bus Frequency Divider Register IBFD Offset 0x00000 Access User read write 0 1 2 3 4 5 6 7 R AD 0 W Reset 0 0 0 0 0 0 0 0 Fi...

Page 1050: ...the SCL Stop hold time Table 32 4 provides the SCL divider and hold values for corresponding values of the ICR The SCL divider multiplied by multiplier factor mul is used to generate I2 C baud rate I...

Page 1051: ...9 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68...

Page 1052: ...ar any currently pending interrupt condition 1 Interrupts from the I2C bus module are enabled An I2C bus interrupt occurs provided the IBIF bit in the status register is also set MS Master Slave Mode...

Page 1053: ...tion TCF Transfer Complete While one byte of data is transferred this bit is cleared It is set by the falling edge of the ninth clock of a byte transfer This bit is valid only during or immediately fo...

Page 1054: ...alue of the R W command bit of the calling address sent from the master This bit is valid only when the I bus is in slave mode a complete address transfer has occurred with an address match and no oth...

Page 1055: ...TART signal slave address transmission data transfer and STOP signal They are described briefly in the following sections and illustrated in Figure 32 10 Offset 0x0005 Access User read write 0 1 2 3 4...

Page 1056: ...es the beginning of a new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states Figure 32 11 Start and Stop conditions SCL SDA Start Signal...

Page 1057: ...rs that come after an address cycle are referred to as data transfers even if they carry sub address information for the slave device Each data byte is 8 bits long Data may be changed only while SCL i...

Page 1058: ...stop driving the SDA output In this case the transition from master to slave mode does not generate a STOP condition Meanwhile a status bit is set by hardware to indicate loss of arbitration 32 4 1 7...

Page 1059: ...4 2 2 Interrupt Description There are five types of internal interrupts in the I2 C The interrupt service routine can determine the interrupt type by reading the status register I2 C Interrupt can be...

Page 1060: ...tted by selecting the master transmitter mode If the device is connected to a multi master bus system the state of the I2 C bus busy bit IBB must be tested to check if the serial bus is free If the bu...

Page 1061: ...determine the direction of the subsequent transfer and the TX bit is programmed accordingly For slave mode data cycles IAAS 0 the SRW bit is not valid The TX bit in the control register should be rea...

Page 1062: ...ing information to IBDR for slave transmits or dummy reading from IBDR in slave receive mode The slave drives SCL low in between byte transfers SCL is released when the IBDR is accessed in the require...

Page 1063: ...itch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS 1...

Page 1064: ...gister works as a disable for the transfer complete interrupt This means that during normal transfers no errors there always is either an interrupt or a request to the DMA controller depending on the...

Page 1065: ...always transmitted by the CPU All subsequent data bytes apart from the two last data bytes can be read by the DMA controller The last two data bytes must be transferred by the CPU Config I2 C for Mast...

Page 1066: ...gister The trigger to exit the DMA mode is that the programmed DMA transfer control descriptor TCD has completed all its transfers to from the I2 C module Config I2C for Master TX interrupt generated...

Page 1067: ...e DMA controller is programmed to signal an interrupt to the CPU which is then responsible for the deassertion of DMAEN This scheme is supported by most systems but can result in a slow reaction time...

Page 1068: ...because those can result in a slow reaction Example latencies for a 32 MHz system with a full speed 32 bit AHB bus and an I2 C connected via half speed IPI bus Accessing the I2 C from the DMA controll...

Page 1069: ...to 0 Different counters associated with different channel groups Channel group is defined based on PWM channel clock Different delay value for each eMIOS flag PIT event 4 bit programmable exponential...

Page 1070: ...l Status Register R W1 0x0000_0000 33 4 1 1 33 4 32 0x0004 CTU_SVR1 Start Value Register 1 R W1 0x0000_0000 33 4 1 2 33 5 32 0x0008 CTU_SVR2 Start Value Register 2 R W1 0x0000_0000 33 4 1 2 33 5 32 0x...

Page 1071: ...VTCFGR82 Event Configuration Register 8 R W1 0x0000_0000 33 4 1 4 33 6 32 0x0054 CTU_EVTCFGR92 Event Configuration Register 9 R W1 0x0000_0000 33 4 1 4 33 6 32 0x0058 CTU_EVTCFGR102 Event Configuratio...

Page 1072: ...1 0x0000_0000 33 4 1 4 33 6 32 0x00B4 0x3FFF Reserved 1 Some bits are read only 2 For eMIOS channels 0 31 3 For PIT3 Offset CTU_BASE 0x0000 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 1073: ...k divided by 64 0111 Clock divided by 128 1000 Clock divided by 256 1001 Clock divided by 512 1010 Clock divided by 1024 1011 1111 Clock divided by 1 no division Offset CTU_BASE 0x0004 CTU_SVR1 0x0008...

Page 1074: ...33 5 Current Value Register CTU_CVRn Table 33 6 CTU_CVRm Register Field Descriptions Bit Description CV 8 0 Current Value These bits contain the current value of the counter The counter starts counti...

Page 1075: ...mmunicate which channel needs to be converted the counter group the start value selection bits and masking bit for that particular event The CTU interfaces between the eMIOS PIT and the ADC and conver...

Page 1076: ...al of an eMIOS or PIT channel The assignment between eMIOS PIT outputs and CTU trigger inputs is defined in Table 33 9 The eMIOS signal FLAG is used in DMA mode to interface with the trigger input of...

Page 1077: ...implemented for only those input flags to which PIT flags are connected The purpose to provide these bits is to have the option of clearing PIT flags by software In summary two levels of arbitration...

Page 1078: ...output of the input events for that counter group A particular counter can only be triggered if some unmasked event is pending in that counter group As soon as a valid input event is detected the cur...

Page 1079: ...the TRGI bit 33 5 5 Halt Request Whenever a halt mode entry request is generated CTU halt bit in the SIU_HLT0 register is set the counters are reset Setting this bit also turns off the clock to the mo...

Page 1080: ...Cross Triggering Unit CTU PXN20 Microcontroller Reference Manual Rev 1 33 12 Freescale Semiconductor...

Page 1081: ...clock from the clock provided to the ADC digital interface The ADC contains analog watchdogs for comparing values of the converted data against user programmed thresholds and interrupt generation base...

Page 1082: ...ered injection Presampling Offset cancellation and offset refresh control External start feature Power down mode Two different abort features allow aborting either a single channel conversion or chain...

Page 1083: ...ask Register 0 R W1 0x0000_0000 34 3 2 8 34 15 32 0x0028 CIMR1 Channel Interrupt Mask Register 1 R W1 0x0000_0000 34 3 2 9 34 15 32 0x002C CIMR2 Channel Interrupt Mask Register 2 R W1 0x0000_0000 34 3...

Page 1084: ...x0000_0000 34 3 2 29 34 35 32 0x00B8 JCMR1 Injected Conversion Mask Register 1 R W1 0x0000_0000 34 3 2 30 34 35 32 0x00BC JCMR2 Injected Conversion Mask Register 2 R W1 0x0000_0000 34 3 2 31 34 36 32...

Page 1085: ...Channel 23 Data Register RO 0x0000_0000 34 3 2 35 34 38 32 0x0160 PRECDATAREG24 Channel 24 Data Register RO 0x0000_0000 34 3 2 35 34 38 32 0x0164 PRECDATAREG25 Channel 25 Data Register RO 0x0000_0000...

Page 1086: ...nnel 54 Data Register RO 0x0000_0000 34 3 2 36 34 39 32 0x01DC INTDATAREG23 Channel 55 Data Register RO 0x0000_0000 34 3 2 36 34 39 32 0x01E0 INTDATAREG24 Channel 56 Data Register RO 0x0000_0000 34 3...

Page 1087: ...00_0000 34 3 2 37 34 39 32 0x024C EXTDATAREG19 Channel 83 Data Register RO 0x0000_0000 34 3 2 37 34 39 32 0x0250 EXTDATAREG20 Channel 84 Data Register RO 0x0000_0000 34 3 2 37 34 39 32 0x0254 EXTDATAR...

Page 1088: ...e 34 2 Main Configuration Register MCR Table 34 2 MCR Field Descriptions Field Description OWREN Overwrite enable 0 Conversion data is discarded 1 Conversion data is overwritten by a newer result WLSI...

Page 1089: ...to be converted by software Resetting this bit has no effect as the injected chain conversion cannot be interrupted CTUEN Cross Triggering Unit enable 0 The cross triggering unit is disabled and the t...

Page 1090: ...d to enter Power Down mode When ADC status is PWDN resetting this bit starts ADC transition to IDLE mode 0 ADC is in normal mode 1 ADC has been requested to power down Address ADC_BASE 0x0004 Access U...

Page 1091: ...g now 1 CTU conversion is occurring Note The CTU is not implemented on the PXN20 CHADDR Channel under measure address This bitfield indicates which channel 0 to 95 is under measure ACKO Auto clock off...

Page 1092: ...is written into the offset register When this bit is set an OFFCANCOVR interrupt has occurred EOFFSET Error in Offset Refresh interrupt EOFFSET flag This interrupt is generated during the offset canc...

Page 1093: ...2 EOC CH1 EOC CH0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 5 Channel Pending Registers 0 CEOCFR0 Table 34 5 CEOCFR0 Field Descr...

Page 1094: ...W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 7 Channel Pending Register 2 CEOCFR2 Table 34 7 CEOCFR2 Field Descriptions Field Desc...

Page 1095: ...When set the JECH interrupt is enabled MSKEOC Mask bit for End of Channel Conversion interrupt EOC When set the EOC interrupt is enabled MSKECH Mask bit for End of Chain Conversion interrupt ECH When...

Page 1096: ...CIM 43 CIM 44 CIM 43 CIM 42 CIM 41 CIM 40 CIM 39 CIM 38 CIM 37 CIM 36 CIM 35 CIM 34 CIM 33 CIM 32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 10 Channel Interrupt Mask Register 1 CIMR1 Table 34...

Page 1097: ...gher than the programmed higher threshold WDGnL This corresponds to the status flag generated when the converted value is lower than the programmed lower threshold Address ADC_BASE 0x0030 Access User...

Page 1098: ...he DMAR0 register contains the DMA Enable bits for group 0 channels channels 0 31 Address ADC_BASE 0x0040 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1099: ...11 DMA 10 DMA 9 DMA 8 DMA 7 DMA 6 DMA 5 DMA 4 DMA 3 DMA 2 DMA 1 DMA 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 15 DMA Channel Select Register 0 DMAR0 Table 34 15 DMAR0 Field Descriptions Fie...

Page 1100: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 17 DMA Channel Select Register 2 DMAR2 Table 34 17 DMAR2 Field Descriptions Field Description DMAn When set channel n is enabled to transfer data in DMA mode Ad...

Page 1101: ...to 95 for threshold comparison Address ADC_BASE 0x0060 THRHLR0 ADC_BASE 0x0064 THRHLR1 ADC_BASE 0x0068 THRHLR2 ADC_BASE 0x006C THRHLR3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0...

Page 1102: ...l voltages group 2 channels PREVAL1 Internal voltage selection for Presampling Selects analog input voltage for presampling from the available four internal voltages group 1 channels PREVAL0 Internal...

Page 1103: ...0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PRES 47 PRES 46 PRES 43 PRES 44 PRES 43 PRES 42 PRES 41 PRES 40 PRES 39 PRES 38 PRES 37 PRES 36 PRES 35 PRES 34 PRES 33 PRES 3...

Page 1104: ...8 29 30 31 R INP LATCH 0 OFFSHIFT 0 INPCMP 0 INPSAMP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 Figure 34 24 Conversion Timing Register 0 CTR0 Table 34 24 CTR0 Field Descriptions Field Description INPLAT...

Page 1105: ...eld Descriptions Field Description INPLATCH Configuration bit for Latching phase duration 0b Latching phase duration is one half clock cycle 1b Latching phase duration is one clock cycle Note The 1b c...

Page 1106: ...b00 or 0b01 0b0000 0100 20 4 24 22 5 168 1 0b10 0b0000 0100 20 4 24 15 168 1 0b10 0b0000 0101 20 4 15 15 135 1 0b11 0b0000 0110 32 4 12 12 132 1 0b11 0b0000 0111 40 4 9 9 128 1 0b11 0b0000 1000 50 4 9...

Page 1107: ...10 37 Tck 30 Tck 1 Tck 68 Tck 1 0b11 0b0010 0111 38 Tck 30 Tck 1 Tck 69 Tck 1 0b11 0b0010 1000 39 Tck 30 Tck 1 Tck 70 Tck 1 0b11 0b0010 1001 40 Tck 30 Tck 1 Tck 71 Tck 1 0b11 0b0010 1010 41 Tck 30 Tck...

Page 1108: ...30 Tck 1 Tck 103 Tck 1 0b11 0b0100 1010 73 Tck 30 Tck 1 Tck 104 Tck 1 0b11 0b0100 1011 74 Tck 30 Tck 1 Tck 105 Tck 1 0b11 0b0100 1100 75 Tck 30 Tck 1 Tck 106 Tck 1 0b11 0b0100 1101 76 Tck 30 Tck 1 Tc...

Page 1109: ...k 30 Tck 1 Tck 138 Tck 1 0b11 0b0110 1101 108 Tck 30 Tck 1 Tck 139 Tck 1 0b11 0b0110 1110 109 Tck 30 Tck 1 Tck 140 Tck 1 0b11 0b0110 1111 110 Tck 30 Tck 1 Tck 141 Tck 1 0b11 0b0111 0000 111 Tck 30 Tck...

Page 1110: ...2 Tck 30 Tck 1 Tck 173 Tck 1 0b11 0b1001 0000 143 Tck 30 Tck 1 Tck 174 Tck 1 0b11 0b1001 0001 144 Tck 30 Tck 1 Tck 175 Tck 1 0b11 0b1001 0010 145 Tck 30 Tck 1 Tck 176 Tck 1 0b11 0b1001 0011 146 Tck 30...

Page 1111: ...7 Tck 30 Tck 1 Tck 208 Tck 1 0b11 0b1011 0011 178 Tck 30 Tck 1 Tck 209 Tck 1 0b11 0b1011 0100 179 Tck 30 Tck 1 Tck 210 Tck 1 0b11 0b1011 0101 180 Tck 30 Tck 1 Tck 211 Tck 1 0b11 0b1011 0110 181 Tck 30...

Page 1112: ...2 Tck 30 Tck 1 Tck 243 Tck 1 0b11 0b1101 0110 213 Tck 30 Tck 1 Tck 244 Tck 1 0b11 0b1101 0111 214 Tck 30 Tck 1 Tck 245 Tck 1 0b11 0b1101 1000 215 Tck 30 Tck 1 Tck 246 Tck 1 0b11 0b1101 1001 216 Tck 30...

Page 1113: ...1 0b11 0b1111 0010 241 Tck 30 Tck 1 Tck 272 Tck 1 0b11 0b1111 0011 242 Tck 30 Tck 1 Tck 273 Tck 1 0b11 0b1111 0100 243 Tck 30 Tck 1 Tck 274 Tck 1 0b11 0b1111 0101 244 Tck 30 Tck 1 Tck 275 Tck 1 0b11 0...

Page 1114: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 27...

Page 1115: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CH79 CH78 CH77 CH76 CH75 CH74 CH73 CH72 CH71 CH70 CH69 CH68 CH67 CH66 CH65 CH64 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F...

Page 1116: ...20 21 22 23 24 25 26 27 28 29 30 31 R CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 31 Injected Conversion Mask Regi...

Page 1117: ...FFSET_WORD field OFFSET_ WORD The offset word coefficient generated at the end of the offset cancellation phase is latched into this register That offset word can be also written by software In that c...

Page 1118: ...9 30 31 R 0 0 0 0 0 0 0 0 PDED W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 35 Power Down Exit Delay Register PDEDR Table 34 37 PDEDR Field Descriptions Field Description PDED The delay between t...

Page 1119: ...result of CTU conversion mode 11 reserved CDATA Channel 0 31 converted data Address See Table 34 1 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 VALID OVERW R...

Page 1120: ...r EXTDATAREGn Table 34 40 EXTDATAREGn Field Descriptions Field Description VALID Used to notify when the data is valid a new value has been written It is automatically cleared when data is read OVERW...

Page 1121: ...rsion must be checked by software This feature is enabled setting the TRGEN bit in the MCR register Two options are available If EDGLEV edge level selection bit in MCR is reset then a rising falling e...

Page 1122: ...us bit is automatically set when the normal conversion starts At the same time MCR NSTART is reset allowing the software to program a new start of conversion In that case the new requested conversion...

Page 1123: ...ons By software setting the MCR JSTART bit the current conversion is suspended and the injected chain is converted At the end of the chain the MSR JSTART bit is reset and the normal chain conversion i...

Page 1124: ...mode is disabled the NSTART bit is automatically reset together with the ABORTCHAIN bit Otherwise if the MODE 1 a new chain conversion is started When an ABORTCHAIN is requested while an injected conv...

Page 1125: ...converted A single channel is converted for each request After performing the conversion the ADC returns the result on the ctu_dataout bus Together with the converted data the ADC outputs two pulses...

Page 1126: ...rmal conversion is ongoing and a pulse is received on the ctu_trigger input line then ongoing channel conversion is aborted and the triggered injected conversion is processed When it is finished norma...

Page 1127: ...sion is fixed In the first case the AD_clock is stretched during the low phase in order to guarantee that constraint Figure 34 43 CTU Control Mode Interface Timings Case 1 Figure 34 44 CTU Control Mod...

Page 1128: ...tage in the presampling state is converted Figure 34 45 Presampling Sequence Figure 34 46 Presampling Sequence with PRECONV 1 Figure 34 47 Presampling Sequence with PREONCE 0 Figure 34 48 Presampling...

Page 1129: ...e of the presampling voltage employed to precharge the ADC hard macrocell is changed as following For the first chain a value of V0 is used for the second chain V1 is used and so on When the presampli...

Page 1130: ...e 34 43 Depending on the MSKWDGnL and MSKWDGnH mask bits in the WTIMR register an interrupt is generated on threshold violation Figure 34 49 Alternate Watchdog Threshold Configuration Figure 34 50 Gua...

Page 1131: ...f the converted voltage lies between the upper and the lower threshold guard window then the output pin and THROP bit in TRCn register keeps its logic value The logic level of the output pin can be pr...

Page 1132: ...e interrupts generated by the analog watchdog are handled by two registers Watchdog Threshold Interrupt Status Register WTISR and Watchdog Threshold Interrupt Mask Register WTIMR in order to check and...

Page 1133: ...ration must be allowed to complete or be aborted manually by resetting the NSTART or OFFCANC bit and only then may the PWDN bit in the MCR register be cleared A normal or an injected conversion can be...

Page 1134: ...Analog to Digital Converter ADC PXN20 Microcontroller Reference Manual Rev 1 34 54 Freescale Semiconductor...

Page 1135: ...and output from the JTAGC is communicated in serial format Chapter 36 Nexus Development Interface NDI includes information relevant to use of the JTAGC including Section 35 6 Initialization Applicati...

Page 1136: ...lly This allows start go commands or step commands to be input to the cores in parallel Commands are shifted in during the JTAG SHIFT_IR state and are executed when the UPDATE_IR state is reached in t...

Page 1137: ...private MCU specific instructions see Table 35 2 Three test data registers a bypass register a boundary scan register and a device identification register A TAP controller state machine that controls...

Page 1138: ...rent Only one test data register path is enabled to shift data between TDI and TDO for each instruction The boundary scan register is enabled for serial access between TDI and TDO when the EXTEST SAMP...

Page 1139: ...ctions to be loaded into the module to select the test to be performed or the test data register to be accessed or both Instructions are shifted in through TDI while the TAP controller is in the Shift...

Page 1140: ...on 35 4 5 Boundary Scan 35 4 Functional Description 35 4 1 JTAGC Reset Configuration While in reset the TAP controller is forced into the test logic reset state thus disabling the test logic and allow...

Page 1141: ...TDO though the selected register starting with the least significant bit as illustrated in Figure 35 5 This applies for the instruction register test data registers and the bypass register Figure 35...

Page 1142: ...chine TEST LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1...

Page 1143: ...GC implements the IEEE 1149 1 2001 defined instructions listed in Table 35 2 This section gives an overview of each instruction Refer to the IEEE 1149 1 2001 standard for more details Table 35 2 JTAG...

Page 1144: ...he JTAGC regains control of the JTAG port during the UPDATE DR state if the PAUSE DR state was entered Auxiliary TAP controllers are held in RUN TEST IDLE while they are inactive See Section 35 5 e200...

Page 1145: ...ls present at the MCU input pins and immediately before the boundary scan register cells at the output pins This sampling occurs on the rising edge of TCK in the capture DR state when the SAMPLE instr...

Page 1146: ...hift register chain contains a serial input and serial output as well as clock and control signals 35 5 e200z0 and e200z6 OnCE Controllers The e200z0 core OnCE controller supports a complete set of Ne...

Page 1147: ...he TDI input of the e200z0 TAP controller The chained configuration allows commands to be loaded into both core s OnCE registers in one shift operation so that both cores can be sent a GO command at t...

Page 1148: ...ated with it 0 1 2 3 4 5 6 7 8 9 R R W GO EX RS W Reset 0 0 0 0 0 0 0 0 1 0 Figure 35 8 OnCE Command Register OCMD Table 35 3 e200z0 and e200z6 OnCE Register Addressing RS Register Selected 000 0000 0...

Page 1149: ...owing sequence is required 1 Set the JCOMP signal to logic 1 thereby enabling the JTAGC TAP controller 2 Load the appropriate instruction for the test or action to be performed 011 0100 Debug Control...

Page 1150: ...IEEE 1149 1 Test Access Port Controller JTAGC PXN20 Microcontroller Reference Manual Rev 1 35 16 Freescale Semiconductor...

Page 1151: ...liary port and the JTAG port The auxiliary port is comprised of 16 output pins and 1 input pin The output pins include 1 message clock out MCKO pin 12 message data out MDO pins 2 message start end out...

Page 1152: ...1 0 MDO 11 0 reset Arbiter Divided system clock e200z6 trace information e200z0 trace information MCKO Input TAP controller Control registers to trace blocks TDO TDI TMS EVTI Reset control Message que...

Page 1153: ...atures are implemented JCOMP TDI TCK TDO TMS JTAG Port Controller JTAGC Program Data Ownership Watchpoint Trace Nexus3 EVTI MSEO 1 0 MCKO MDO 11 0 Nexus Port Controller EVTO AXBS Peripheral Bridge SRA...

Page 1154: ...port features Nexus3 IEEE ISTO 5001 2003 standard class 3 compliant Program trace via branch trace messaging BTM Branch trace messaging displays program flow discontinuities direct branches indirect b...

Page 1155: ...ility for an event out signal from either the e200z6 Nexus3 or e200z0 Nexus2 to generate a debug request to the other core thus allowing both cores to enter debug mode within a short period of each ot...

Page 1156: ...f trace messages and Nexus access to memory mapped resources when censorship is enabled 36 2 2 6 Halt Mode Halt mode logic is implemented in the Nexus port controller NPC When a request is made to ent...

Page 1157: ...Table 36 3 Detailed sequences for Nexus3 register access are described in Section 36 6 10 8 IEEE 1149 1 JTAG RD WR Sequences Detailed sequences for Nexus2 register access are described in Section 36 7...

Page 1158: ...x13 36 6 8 4 36 36 0x0A e200z6 Read Write Access Data Nexus3_RWD 0x14 0x15 36 6 8 5 36 36 0x0B e200z6 Watchpoint Trigger PPC_WT 0x16 0x17 36 6 8 6 36 38 0x0D e200z6 Data Trace Control PPC_DTC 0x1A 0x1...

Page 1159: ...C IEEE 1149 1 2001 JTAG TAP 36 4 1 2 TAP Sharing Each of the individual Nexus blocks on the MCU implements a TAP controller for accessing its registers The JTAGC controls the ownership of the TAP so t...

Page 1160: ...CLK speed Table 36 5 shows the MCKO_DIV encodings In this table SYS_CLK represents the system clock frequency 36 4 1 5 Nexus Messaging Most of the messages transmitted by the NDI include a SRC field T...

Page 1161: ...r a pulse of the devt2 signal causes a debug event to occur In this case only one external EVTO signal is generated and each core controls whether or not EVTO causes a debug event to occur Interconnec...

Page 1162: ...z6 into debug mode Assert System Reset Enable Nexus Select NPC PCR Register and Configure FPM MCK_EN EVT_EN and MCK fields Access Nexus Dev Control Register 1 Configure EOC Field EVTO Control Select O...

Page 1163: ...e NPC DID are the same as the JTAGC device identification register 36 5 1 NPC Overview The PXN20 incorporates multiple modules that require development support Each of these modules implements a devel...

Page 1164: ...ection consists of NPC register descriptions 36 5 4 1 Bypass Register The bypass register is a single bit shift register path selected for serial data transfer between TDI and TDO when the BYPASS inst...

Page 1165: ...AG TAP This register is read only 3 2 1 0 R Previous Instruction Opcode W Instruction Opcode Reset BYPASS Instruction Opcode 0xF Figure 36 5 4 Bit Instruction Register Reg Index 0x00 Access User read...

Page 1166: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LP_DBG _EN 0 0 0 0 0 SLEEP _SYNC 0 0 0 0 0 0 0 0 PSTAT _EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36 7 Port Configuration...

Page 1167: ...t sleep mode 0 No sleep mode entry pending 1 Sleep mode entry pending Note During sleep entry the device sets the SLEEP_SYNC bit The debug tool then clears this bit to enter low power mode The bit cha...

Page 1168: ...e individual modules and arbitrates for access to the port Additional information about the auxiliary port is found in Section 35 1 1 1 Individual and Multi Core Debug 36 5 5 2 1 Output Message Protoc...

Page 1169: ...ly when following a fixed length field Super fields must end on a port boundary When a variable length field is sized such that it does not end on a port boundary it is necessary to extend and zero fi...

Page 1170: ...E instruction then grants access to NPC registers Retrieving Device IDCODE The Nexus TAP controller does not implement the IDCODE instruction However the device identification message can be output by...

Page 1171: ...lowed by a 7 bit register address index as illustrated in Figure 36 12 The read write control bit is set to 1 for writes and 0 for reads Table 36 11 Loading NEXUS ENABLE Instruction Clock TDI TMS IEEE...

Page 1172: ...st is NPC Nexus3 and Nexus2 This arbitration mechanism is controlled internally and is not programmable by tools or the user 36 5 5 2 5 Nexus JTAG Port Sharing Each of the individual Nexus modules on...

Page 1173: ...g of the EVTO output between all Nexus clients that produce an EVTO signal EVTO is driven for one MCKO period whenever any module drives its EVTO The sharing mechanism is a logical AND of all incoming...

Page 1174: ...core in compliance with the IEEE ISTO Nexus 5001 2003 standard This module provides development support capabilities without requiring the use of address and data pins for internal visibility A portio...

Page 1175: ...he number of sequential instructions executed between each taken branch Client A functional block on an embedded processor that requires development visibility and controllability Examples are a centr...

Page 1176: ...Trace Messaging Higher speed data input output via the auxiliary port Registers for Program Trace Data Trace Ownership Trace and Watchpoint Trigger All features controllable and configurable via the J...

Page 1177: ...are not available for reads or writes 36 6 6 TCODEs Supported by Nexus3 The Nexus3 pins allow for flexible transfer operations via public messages A TCODE defines the transfer format the number and or...

Page 1178: ...CODE Fixed error code Program Trace Direct Branch Message w Sync1 6 6 TCODE Fixed TCODE number 11 0x0B 4 4 SRC Fixed source processor identifier 1 8 I CNT Variable sequential instructions executed sin...

Page 1179: ...source processor identifier 1 8 I CNT Variable sequential instructions executed since last taken branch 1 32 U ADDR Variable unique part of target address for taken branches exceptions 1 32 HIST Varia...

Page 1180: ...Invalid access opcode Nexus register unimplemented 00110 Watchpoint overrun 00111 Program Trace or Data Trace and Ownership Trace overrun 01000 Program Trace or Data Trace or Ownership Trace and Watc...

Page 1181: ...3 module 1110 Entry into a VLE page from a non VLE page 1111 Entry into a non VLE page from a VLE page 1 The device enters Low Power Mode when the Nexus stall mode is enabled Nexus3_DC1 OVC 0b011 and...

Page 1182: ...Reserved 0x28 0x7E 0x29 0x7F Nexus Reg 0x02 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R OPC MCK_DIV EOC 0 PTM WEN 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1183: ...TI Control 00 EVTI is used for synchronization program trace data trace 01 EVTI is used for debug request 1X Reserved TM Trace Mode Any or all of the TM bits may set enabling one or more traces 000 No...

Page 1184: ...configure the EVTO watchpoint 0000_0000 No Watchpoints trigger EVTO 1xxx_xxxx Watchpoint 0 IAC1 from Nexus1 triggers EVTO x1xx_xxxx Watchpoint 1 IAC2 from Nexus1 triggers EVTO xx1x_xxxx Watchpoint 2 I...

Page 1185: ...mode 01 CPU in halted state 10 CPU in stopped state 11 Reserved CHK CPU Checkstop Status 0 CPU not in checkstop state 1 CPU in checkstop state Nexus Reg 0x7 Access User read write 31 30 29 28 27 26 25...

Page 1186: ...rst Control 0 Module accesses are single bus cycle at a time 1 Module accesses are performed as burst operation CNT Access Control Count Number of accesses of word size SZ ERR Read Write Access Error...

Page 1187: ...ess Data Register RWD Table 36 25 RWD Data Placement for Transfers Transfer Size and byte offset RWA 2 0 RWCS SZ RWD 31 24 23 16 15 8 7 0 Byte xxx 000 X Half Word xx0 001 X X Word x00 010 X X X X Doub...

Page 1188: ...access ensure that TCK continues to run for at least one TCK after leaving the Update DR state This can be just a TCK with TMS low while in the Run Test Idle state or by continuing with the next Nexus...

Page 1189: ...PTS Program Trace Start Control 000 Trigger disabled 001 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Ne...

Page 1190: ...exus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watchpoint 5 DAC2 from Nexus1 111...

Page 1191: ...ace on address outside of range 6 RC2 Range control 2 0 Condition trace on address within range 1 Condition trace on address outside of range 3 DI1 Data access instruction access trace 1 0 Condition t...

Page 1192: ...er to Table 36 2 For the Nexus3 module the OCMD value is 0b00_0111_1100 Once the ACCESS_AUX_TAP_Z6 instruction has been loaded the JTAG OnCE port allows tool target communications with all Nexus3 regi...

Page 1193: ...1 Debug Status Messages Debug Status Messages report low power mode and debug status Debug Status Messages are enabled when Nexus 3 is enabled Entering exiting Debug Mode as well as entering a Low Po...

Page 1194: ...e following format Figure 36 26 Ownership Trace Message Format 36 6 10 2 3 OTM Error Messages An error message occurs when a new message cannot be queued due to the message queue being full The FIFO d...

Page 1195: ...1 Branch Trace Messaging BTM Traditional branch trace messaging facilitates program trace by providing the following types of information Messaging for taken direct branches includes how many sequenti...

Page 1196: ...redicated instruction tracking and save bandwidth since only indirect branches cause messages to be queued BTM Using Traditional Program Trace Messages Based on the PTM bit in the DC register DC PTM p...

Page 1197: ...mined at run time interrupts and exceptions If DC PTM is set indirect branch information is messaged out in the following format Figure 36 28 Indirect Branch Message History Format Indirect Branch Mes...

Page 1198: ...Resource Full messages Program Correlation Messages Program correlation messages are used to correlate events to the program flow that may not be associated with the instruction stream The following...

Page 1199: ...n the proper context Program correlation is messaged out in the following format Figure 36 32 Program Correlation Message Format BTM Overflow Error Messages An error message occurs when a new message...

Page 1200: ...gister have enabled this feature Upon direct indirect branch after the sequential instruction counter has expired indicating 255 instructions have occurred between branches Upon direct indirect branch...

Page 1201: ...on initiates a direct indirect branch with sync message upon the next direct indirect branch if program trace is enabled and the EIC bits of the DC1 register have enabled this feature Sequential Instr...

Page 1202: ...e address with the previously decoded address gives the current address Previous address A1 0x0003_FC01 New address A2 0x0003_F365 Figure 36 36 Relative Address Generation and Re creation Execution Mo...

Page 1203: ...zero 0 is shifted into the history buffer on any instruction whose predicate condition executed as false as well as on branches not taken This includes indirect as well as direct branches not taken F...

Page 1204: ...ss 0xA5 01 11 00 0000 0010 0000 0000 1010 0101 0000 0000 0100 MDO 1 0 TCODE 28 MCKO MSEO Source Processor 0b0000 Number of Sequential Instructions 0 Relative Address 0xA5 Branch History 0b1010_0101 wi...

Page 1205: ...r data visibility for the incorporated data cache Only e200z6 CPU initiated accesses are traced Data trace messaging can be enabled in one of two ways Setting the TM field of the DC1 register to enabl...

Page 1206: ...a value The debug development tool needs to distinguish the two cases based on the family of Zen processor DTM Overflow Error Messages An error message occurs when a new message cannot be queued due t...

Page 1207: ...the first data trace message is a synchronization message if the EIC bits of the DC1 register have enabled this feature Upon data trace write read after the previous DTM message was lost due to an at...

Page 1208: ...t data trace message is converted to a data write read with sync message Queue Overrun An error message occurs when a new message cannot be queued due to the message queue being full The FIFO discards...

Page 1209: ...is word and one with a size encoding for the portion that crossed the boundary that is 3 byte NOTE An STM to the cache s store buffer within the data trace range initiates a DTM message If the corres...

Page 1210: ...standard Nexus3 is not compliant with Class4 breakpoint watchpoint requirements defined in the standard The breakpoint watchpoint control register is not implemented MCKO MSEO 1 0 TCODE 5 Source Proc...

Page 1211: ...Watchpoint Error Message An error message occurs when a new message cannot be queued due to the message queue being full The FIFO discards messages until it has completely emptied the queue Once empt...

Page 1212: ...ltiple configurable priority levels Memory mapped registers and other non cached memory can be accessed via the standard memory map settings All accesses are setup and initiated by the read write acce...

Page 1213: ...ster RWD through the access method outlined in Section 36 6 9 Nexus3 Register Access via JTAG OnCE using the Nexus register index of 0xA see Table 36 19 Configure as follows Write Data 0xnnnn_nnnn wri...

Page 1214: ...rite access address register RWA For each access within the burst the address from the RWA register is incremented to the next double word size specified in the SZ field modulo the length of the burst...

Page 1215: ...d size specified in the SZ field and the number from the CNT field is decremented 3 The data can then be read from the read write access data register RWD through the access method outlined in Section...

Page 1216: ...error Access Termination The following cases are defined for sequences of the read write protocol that differ from those described in the above sections 1 If the AC bit in the RWCS register is set to...

Page 1217: ...significant bits where Tx TCODE number fixed Sx Source processor fixed Ix Number of instructions variable Table 36 38 Indirect Branch Message Example 12 MDO 2 MSEO Clock MDO 11 0 MSEO 1 0 State 11 10...

Page 1218: ...Clock MDO 11 0 MSEO 1 0 State 11 10 9 8 7 6 5 4 3 2 1 0 0 X X X X X X X X X X X X 1 1 Idle or end of last message 1 Z1 Z0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start Message 2 0 0 0 0 0 0 0 A3 A2 A1 A0 Z...

Page 1219: ...egister RWA 2 37 Write RWA initialize starting read address data input on TDI 3 13 Nexus Command write to read write control status register RWCS 4 37 Write RWCS initialize read access mode and CNT va...

Page 1220: ...n e200z0 processors 36 7 1 Nexus2 Introduction This section defines the auxiliary pin functions transfer protocols and standard development features of the Nexus2 module The development features suppo...

Page 1221: ...lity of which process ID or operating system task is activated An ownership trace message is transmitted when a new process task is activated allowing the development tool to trace ownership flow Run...

Page 1222: ...not available for reads or writes 36 7 5 TCODEs Supported by Nexus2 The Nexus2 pins allow for flexible transfer operations via public messages A TCODE defines the transfer format the number and or si...

Page 1223: ...e processor identifier 4 4 RCODE Fixed resource code Refer to RCODE values in Table 36 46 indicates which resource is the cause of this message 1 32 RDATA Variable branch predicate instruction history...

Page 1224: ...e shaded TCODEs above are not messaged out Table 36 45 Error Code Encoding TCODE 8 Error Code ECODE Description 00000 Ownership trace overrun 00001 Program trace overrun 00010 Reserved 00011 Read writ...

Page 1225: ...nters Low Power Mode when the Nexus stall mode is enabled NEXUS2_DC1 OVC 0b011 and a trace message is in danger of over flowing the Nexus queue 0010 0011 Reserved for future functionality 0100 Disabli...

Page 1226: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36 53 Development Control Register 1 DC1 Table 36 49 DC1 Field Descriptions Field Description OPC1 Output port mode control 0 Reduced port mode configuration not ava...

Page 1227: ...re shown for clarity These functions are controlled globally by the NPC port control register PCR These bits are writable in the PCR but have no effect Nexus Reg 0x3 Access User read write 31 30 29 28...

Page 1228: ...bus either while the processor is halted or during runtime The RWCS register also provides read write access status information as shown in Table 36 52 Nexus Reg 0x4 Access User read only 31 30 29 28...

Page 1229: ...n AC Access control 0 End access 1 Start access RW Read write select 0 Read access 1 Write access SZ 2 0 Word size 000 8 bit byte 001 16 bit half word 010 32 bit word 011 Reserved 100 111 Reserved def...

Page 1230: ...pleted without error 0 0 Read access error has occurred Write access error has occurred 1 0 Read access completed without error Write access has not completed 0 1 Not allowed Not allowed 1 1 Nexus Reg...

Page 1231: ...ring trace messages Table 36 56 details the watchpoint trigger register fields Table 36 55 RWD data placement for Transfers Transfer Size and byte offset RWA 2 0 RWD 31 24 23 16 15 8 7 0 Byte 000 000...

Page 1232: ...2 passes through the data scan DR path of the JTAG state machine see 36 6 10 8 1 The first pass through the DR selects the Nexus2 register to be accessed by providing an index see Table 36 48 and the...

Page 1233: ...ort low power mode and debug status Entering exiting debug mode as well as entering a low power mode triggers a debug status message Debug status information is sent out in the following format Figure...

Page 1234: ...the following format Figure 36 61 Ownership Trace Message Format 36 7 9 2 3 OTM Error Messages An error message occurs when a new message cannot be queued due to the message queue being full The FIFO...

Page 1235: ...Branch Trace Messaging BTM Traditional branch trace messaging facilitates program trace by providing the following types of information Messaging for taken direct branches includes how many sequential...

Page 1236: ...nd save bandwidth since only indirect branches cause messages to be queued BTM Using Traditional Program Trace Messages Based on the PTM bit in the DC register DC PTM program tracing can utilize eithe...

Page 1237: ...at run time interrupts and exceptions If DC PTM is set indirect branch information is messaged out in the following format Figure 36 63 Indirect Branch Message History Format Indirect Branch Messages...

Page 1238: ...ssages Program correlation messages are used to correlate events to the program flow that may not be associated with the instruction stream The following events result in a PCM when program trace is e...

Page 1239: ...on Message Format BTM Overflow Error Messages An error message occurs when a new message cannot be queued due to the message queue being full The FIFO discards incoming messages until it has completel...

Page 1240: ...ntial instruction counter has expired indicating 255 instructions have occurred between branches Upon direct indirect branch after a BTM message was lost due to an attempted access to a secure memory...

Page 1241: ...hronization occurs periodically after 255 program trace messages have been queued A direct indirect branch with sync message is queued The periodic program trace message counter then resets Event In I...

Page 1242: ...the least significant bit of the reconstructed address field A value of 0 indicates that preceding instruction count and history information should be interpreted in a non VLE context A value of 1 ind...

Page 1243: ...number of sequential instructions or non taken branches in between direct indirect branch messages For branch history messages I CNT represents the number of instructions executed since the last taken...

Page 1244: ...al Instructions 0 Relative Address 0xA5 Branch History 0b1010_0101 with Stop 11 01 00 00 00 01 01 10 10 01 01 10 10 00 00 Note This is representative only The PXN20 supports only Full Port Mode with 1...

Page 1245: ...put clock MCKO Watchpoint information is messaged out in the following format Figure 36 76 Watchpoint Message Format 36 7 9 4 3 Watchpoint Error Message An error message occurs when a new message cann...

Page 1246: ...tiple configurable priority levels Memory mapped registers and other non cached memory can be accessed via the standard memory map settings All accesses are setup and initiated by the read write acces...

Page 1247: ...ata register RWD through the access method outlined in Section 36 7 8 Nexus2 Register Access via JTAG OnCE using the Nexus register index of 0xA see Table 36 48 Configure as follows Write Data 0xnnnn_...

Page 1248: ...NT 0x0000 or 0x0001 single access NOTE Access Count CNT of 0x0000 or 0x0001 performs a single access 3 The Nexus2 module then arbitrates for the system bus and the read data is transferred from the sy...

Page 1249: ...The following cases are defined for sequences of the read write protocol that differ from those described in the above sections 1 If the AC bit in the RWCS register is set to start read write accesses...

Page 1250: ...d Ix Number of instructions variable Table 36 64 an example data write message with 12 MDO 2 MSEO configuration Table 36 62 Indirect Branch Message Example 12 MDO 2 MSEO Clock MDO 11 0 MSEO 1 0 State...

Page 1251: ...1 End Packet 3 X X X X D7 D6 D5 D4 D3 D2 D1 D0 1 1 End Packet End Message Table 36 65 Accessing Internal Nexus2 Registers via JTAG OnCE Step TMS Pin Description 1 1 IDLE SELECT DR_SCAN 2 0 SELECT DR_S...

Page 1252: ...ug classifications according to the Nexus consortium are shown in Figure 36 80 Table 36 66 Accessing Memory Mapped Resources Reads Step TCLK clocks Description 1 13 Nexus Command write to read write a...

Page 1253: ...Data trace read write optional optional optional Data acquisition optional optional optional Memory substitution X Complex triggering X X X External memory substitution optional Optional feature Stati...

Page 1254: ...on every device of the family and are not multiplexed The EVTO and EVTI functions are bonded out on dedicated 3 3 V pads on the 256MAPBGA They are provided on the 208MAPBGA on 5 V pads multiplexed wi...

Page 1255: ...be used for debug purposes only after the activation of the Nexus controller Such activation is consequent to a certain sequence given by the debugger MDO 9 N2 3 Aux port Dedicated NO Dedicated MDO 10...

Page 1256: ...36 11 1 208 MAPBGA Package Debug Method The 208MAPBGA package provides only the Nexus class 1 debug method based on IEEE1149 1 standard Figure 36 82 shows an example Figure 36 82 Nexus Class 1 Debuggi...

Page 1257: ...Nexus Development Interface NDI PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 36 107...

Page 1258: ...Nexus Development Interface NDI PXN20 Microcontroller Reference Manual Rev 1 36 108 Freescale Semiconductor...

Page 1259: ...Page A 3 MLB_DIM Configuration 0xC3F8_4000 Page A 8 I2 C_C 0xC3F8_8000 Page A 11 I2 C_D 0xC3F8_C000 Page A 11 DSPI_C 0xC3F9_0000 Page A 12 DSPI_D 0xC3F9_4000 Page A 13 eSCI_J 0xC3FA_0000 Page A 14 eSC...

Page 1260: ...B_8000 Page A 61 eSCI_H 0xFFFB_C000 Page A 62 FlexCan_A 0xFFFC_0000 Page A 62 FlexCan_B 0xFFFC_4000 Page A 67 FlexCan_C 0xFFFC_8000 Page A 72 FlexCan_D 0xFFFC_C000 Page A 76 FlexCan_E 0xFFFD_0000 Page...

Page 1261: ...0x0002_0000 0x0002_FFFF 64 Program Data Flash 0x0003_0000 0x0003_FFFF 64 Program Data Flash 0x0004_0000 0x0005_FFFF 128 Program Data Flash 0x0006_0000 0x0007_FFFF 128 Program Data Flash 0x0008_0000 0x...

Page 1262: ...3FA_3FFF 16 eSCI_J X 0xC3FA_4000 0xC3FA_7FFF 16 eSCI_K X 0xC3FA_8000 0xC3FA_BFFF 16 eSCI_L X 0xC3FA_C000 0xC3FA_FFFF 16 eSCI_M X 0xC3FB_0000 0xC3FB_3FFF 16 Reserved 0xC3FB_4000 0xC3FB_7FFF 16 Reserved...

Page 1263: ...xFFF4_3FFF 16 ECSM 0xFFF4_4000 0xFFF4_7FFF 16 eDMA Channels 16 31 0xFFF4_8000 0xFFF4_BFFF 16 INTC 0xFFF4_C000 0xFFF4_FFFF 16 FEC X 0xFFF5_0000 0xFFF7_FFFF 192 Reserved 0xFFF8_0000 0xFFF8_3FFF 16 ADC_A...

Page 1264: ...FlexCan_E 0xFFFD_4000 0xFFFD_7FFF 16 FlexCan_F X 0xFFFD_8000 0xFFFD_BFFF 16 CTU_A X 0xFFFD_C000 0xFFFD_FFFF 16 DMA Multiplexer 0xFFFE_0000 0xFFFE_3FFF 16 PIT 0xFFFE_4000 0xFFFE_7FFF 16 eMIOS_A Channe...

Page 1265: ...5 0x000A_0000 H1 0x000C_0000 H2 6 0x000E_0000 H3 0x0010_0000 H4 7 0x0012_0000 H5 0x0014_0000 H6 8 0x0016_0000 H7 0x0018_0000 0xF0_FFFF Reserved 0x00FF_8000 0x00FF_FDD7 General use S All1 1 For read wh...

Page 1266: ...020 SBCR Synchronous Base Address Configuration Register R W 0x0000_0000 27 3 2 6 27 14 0x0024 ABCR Asynchronous Base Address Configuration Register R W 0x0000_0000 27 3 2 7 27 14 0x0028 CBCR Control...

Page 1267: ...CR5 Channel 5 Next Buffer Configuration Register R W 0x0000_0000 27 3 2 14 27 23 0x00A0 CECR6 Channel 6 Entry Configuration Register R W 0x0000_0000 27 3 2 11 27 17 0x00A4 CSCR6 Channel 6 Status Confi...

Page 1268: ...0 27 3 2 11 27 17 0x0114 CSCR13 Channel 13 Status Configuration Register R W 0x8000_0000 27 3 2 12 27 19 0x0118 CCBCR13 Channel 13 Current Buffer Configuration Register R W 0x0000_0000 27 3 2 13 27 22...

Page 1269: ...CBCR14 Local Channel 14 Buffer Configuration Register R W 0x0803_E1C0 27 3 2 15 27 24 0x02BC LCBCR15 Local Channel 15 Buffer Configuration Register R W 0x0803_E1E0 27 3 2 15 27 24 0x02C0 0x3FFF Reserv...

Page 1270: ...0x002C DSPI_SR DSPI status register R 0x0000_0000 30 3 2 4 30 16 0x0030 DSPI_RSER DSPI DMA interrupt request select and enable register R W 0x0000_0000 30 3 2 5 30 18 FIFO Registers 0x0034 DSPI_PUSHR...

Page 1271: ...register 4 R W 0x7800_0000 30 3 2 3 30 10 0x0020 DSPI_CTAR5 DSPI clock and transfer attributes register 5 R W 0x7800_0000 30 3 2 3 30 10 0x0024 DSPI_CTAR6 DSPI clock and transfer attributes register...

Page 1272: ...31 6 0x0002 eSCI_CR1 eSCI control register 1 R W 0x0000 31 3 2 2 31 6 0x0004 eSCI_CR2 eSCI control register 2 R W 0x0200 31 3 2 3 31 8 0x0006 eSCI_SDR eSCI data register R W 0x0000 31 3 2 4 31 10 0x00...

Page 1273: ...F Reserved 0xC3FA_8000 eSCI_L Chapter 31 Enhanced Serial Communication Interface eSCI 0x0000 eSCI_BRR eSCI baud rate register R W 0x0004 31 3 2 1 31 6 0x0002 eSCI_CR1 eSCI control register 1 R W 0x000...

Page 1274: ...SCI_LPR eSCI LIN CRC polynomial register R W 0xC599 31 3 2 11 31 18 0x001A eSCI_CR3 eSCI control register 3 R W 0x0000 31 3 2 12 31 18 0x001C 0x3FFF Reserved 0xC3FB_0000 0xC3FD_BFFF Reserved 0xC3FD_C0...

Page 1275: ...SLTCTBR Slot counter channel B register R 0x0000 26 5 2 26 26 39 0x0038 RTCORVR Rate correction value register R 0x0000 26 5 2 27 26 39 0x003A OFCORVR Offset correction value register R 0x0000 26 5 2...

Page 1276: ...0x0074 SSR6 Slot status register 6 R 0x0000 26 5 2 46 26 53 0x0076 SSR7 Slot status register 7 R 0x0000 26 5 2 46 26 53 0x0078 SSCR0 Slot status counter register 0 R 0x0000 26 5 2 47 26 54 0x007A SSC...

Page 1277: ...3 26 67 0x00A6 PCR3 Protocol configuration register 3 R W 0x0000 26 5 2 67 4 26 67 0x00A8 PCR4 Protocol configuration register 4 R W 0x0000 26 5 2 67 5 26 67 0x00AA PCR5 Protocol configuration registe...

Page 1278: ...n register 24 R W 0x0000 26 5 2 67 25 26 72 0x00D2 PCR25 Protocol configuration register 25 R W 0x0000 26 5 2 67 26 26 72 0x00D4 PCR26 Protocol configuration register 26 R W 0x0000 26 5 2 67 27 26 72...

Page 1279: ...e buffer frame ID register 3 R W 0x0UUU 26 5 2 70 26 76 0x011E MBIDXR3 Message buffer index register 3 R W 0x00UU 26 5 2 71 26 76 0x0120 MBCCSR4 Message buffer configuration control status register 4...

Page 1280: ...register 11 R W 0x0000 26 5 2 68 26 73 0x015A MBCCFR11 Message buffer cycle counter filter register 11 R W 3 26 5 2 69 26 75 0x015C MBFIDR11 Message buffer frame ID register 11 R W 0x0UUU 26 5 2 70 26...

Page 1281: ...68 26 73 0x0192 MBCCFR18 Message buffer cycle counter filter register 18 R W 3 26 5 2 69 26 75 0x0194 MBFIDR18 Message buffer frame ID register 18 R W 0x0UUU 26 5 2 70 26 76 0x0196 MBIDXR18 Message b...

Page 1282: ...2 68 26 73 0x01CA MBCCFR25 Message buffer cycle counter filter register 25 R W 3 26 5 2 69 26 75 0x01CC MBFIDR25 Message buffer frame ID register 25 R W 0x0UUU 26 5 2 70 26 76 0x01CE MBIDXR25 Message...

Page 1283: ...2 68 26 73 0x0202 MBCCFR32 Message buffer cycle counter filter register 32 R W 3 26 5 2 69 26 75 0x0204 MBFIDR32 Message buffer frame ID register 32 R W 0x0UUU 26 5 2 70 26 76 0x0206 MBIDXR32 Message...

Page 1284: ...2 68 26 73 0x023A MBCCFR39 Message buffer cycle counter filter register 39 R W 3 26 5 2 69 26 75 0x023C MBFIDR39 Message buffer frame ID register 39 R W 0x0UUU 26 5 2 70 26 76 0x023E MBIDXR39 Message...

Page 1285: ...68 26 73 0x0272 MBCCFR46 Message buffer cycle counter filter register 46 R W 3 26 5 2 69 26 75 0x0274 MBFIDR46 Message buffer frame ID register 46 R W 0x0UUU 26 5 2 70 26 76 0x0276 MBIDXR46 Message b...

Page 1286: ...68 26 73 0x02AA MBCCFR53 Message buffer cycle counter filter register 53 R W 3 26 5 2 69 26 75 0x02AC MBFIDR53 Message buffer frame ID register 53 R W 0x0UUU 26 5 2 70 26 76 0x02AE MBIDXR53 Message b...

Page 1287: ...68 26 73 0x02E2 MBCCFR60 Message buffer cycle counter filter register 60 R W 3 26 5 2 69 26 75 0x02E4 MBFIDR60 Message buffer frame ID register 60 R W 0x0UUU 26 5 2 70 26 76 0x02E6 MBIDXR60 Message b...

Page 1288: ...68 26 73 0x031A MBCCFR67 Message buffer cycle counter filter register 67 R W 3 26 5 2 69 26 75 0x031C MBFIDR67 Message buffer frame ID register 67 R W 0x0UUU 26 5 2 70 26 76 0x031E MBIDXR67 Message b...

Page 1289: ...68 26 73 0x0352 MBCCFR74 Message buffer cycle counter filter register 74 R W 3 26 5 2 69 26 75 0x0354 MBFIDR74 Message buffer frame ID register 74 R W 0x0UUU 26 5 2 70 26 76 0x0356 MBIDXR74 Message bu...

Page 1290: ...2 68 26 73 0x038A MBCCFR81 Message buffer cycle counter filter register 81 R W 3 26 5 2 69 26 75 0x038C MBFIDR81 Message buffer frame ID register 81 R W 0x0UUU 26 5 2 70 26 76 0x038E MBIDXR81 Message...

Page 1291: ...68 26 73 0x03C2 MBCCFR88 Message buffer cycle counter filter register 88 R W 3 26 5 2 69 26 75 0x03C4 MBFIDR88 Message buffer frame ID register 88 R W 0x0UUU 26 5 2 70 26 76 0x03C6 MBIDXR88 Message b...

Page 1292: ...68 26 73 0x03FA MBCCFR95 Message buffer cycle counter filter register 95 R W 3 26 5 2 69 26 75 0x03FC MBFIDR95 Message buffer frame ID register 95 R W 0x0UUU 26 5 2 70 26 76 0x03FE MBIDXR95 Message b...

Page 1293: ...73 0x0432 MBCCFR102 Message buffer cycle counter filter register 102 R W 3 26 5 2 69 26 75 0x0434 MBFIDR102 Message buffer frame ID register 102 R W 0x0UUU 26 5 2 70 26 76 0x0436 MBIDXR102 Message bu...

Page 1294: ...8 26 73 0x046A MBCCFR109 Message buffer cycle counter filter register 109 R W 3 26 5 2 69 26 75 0x046C MBFIDR109 Message buffer frame ID register 109 R W 0x0UUU 26 5 2 70 26 76 0x046E MBIDXR109 Messag...

Page 1295: ...26 73 0x04A2 MBCCFR116 Message buffer cycle counter filter register 116 R W 3 26 5 2 69 26 75 0x04A4 MBFIDR116 Message buffer frame ID register 161 R W 0x0UUU 26 5 2 70 26 76 0x04A6 MBIDXR116 Message...

Page 1296: ...8 26 73 0x04DA MBCCFR123 Message buffer cycle counter filter register 123 R W 3 26 5 2 69 26 75 0x04DC MBFIDR123 Message buffer frame ID register 123 R W 0x0UUU 26 5 2 70 26 76 0x04DE MBIDXR123 Messag...

Page 1297: ...1 16 4 0x0004 0x000F Reserved 0x0010 XBAR_SGPCR0 General purpose control register slave port 0 R W 0x0000_0000 16 2 1 2 16 6 0x0004 0x000F Reserved 0x0100 XBAR_MPR1 Master priority register slave por...

Page 1298: ...1 R W 0x00 15 3 2 1 15 4 0x0002 SEMA4_Gate02 Semaphores gate 2 R W 0x00 15 3 2 1 15 4 0x0003 SEMA4_Gate03 Semaphores gate 3 R W 0x00 15 3 2 1 15 4 0x0004 SEMA4_Gate04 Semaphores gate 4 R W 0x00 15 3 2...

Page 1299: ...t 0 R 3 18 3 2 2 18 6 0x0014 MPU_EDR0 MPU error detail register MPU port 0 R 3 18 3 2 3 18 7 0x0018 MPU_EAR1 MPU error address register MPU port 1 R 3 18 3 2 2 18 6 0x001C MPU_EDR1 MPU error detail re...

Page 1300: ...D alternate access control 4 R W 3 18 3 2 5 18 13 0x0814 MPU_RGDAAC5 MPU RGD alternate access control 5 R W 3 18 3 2 5 18 13 0x0818 MPU_RGDAAC6 MPU RGD alternate access control 6 R W 3 18 3 2 5 18 13...

Page 1301: ...gister R W 0x0000_0000 21 3 2 5 21 5 0x001C Reserved 0x0020 STM_CCR1 STM channel 1 control register R W 0x0000_0000 21 3 2 3 21 4 0x0024 STM_CIR1 STM channel 1 interrupt register R W 0x0000_0000 21 3...

Page 1302: ...F Reserved 0xFFF4_4000 eDMA Chapter 24 Enhanced Direct Memory Access Controller eDMA 0x0000 EDMA_CR eDMA control register R W 0x0000_0400 24 3 2 1 24 8 0x0004 EDMA_ESR eDMA error status register R 0x0...

Page 1303: ...24 3 2 16 24 22 0x0108 EDMA_CPR8 eDMA channel 8 priority register R W 0x08 24 3 2 16 24 22 0x0109 EDMA_CPR9 eDMA channel 9 priority register R W 0x09 24 3 2 16 24 22 0x010A EDMA_CPR10 eDMA channel 10...

Page 1304: ...4 23 0x10A0 TCD05 eDMA transfer control descriptor 05 R W 1 24 3 2 17 24 23 0x10C0 TCD06 eDMA transfer control descriptor 06 R W 1 24 3 2 17 24 23 0x10E0 TCD07 eDMA transfer control descriptor 07 R W...

Page 1305: ...C0 INTC current priority register for processor 0 Z6 R W 0x0000_000F 10 3 2 2 10 10 0x00C INTC_CPR_PRC1 INTC current priority register for processor 1 Z0 R W 0x0000_000F 10 3 2 3 10 12 0x0010 INTC_IAC...

Page 1306: ...riority select register 72 75 R W 0x0000_0000 10 3 2 9 10 16 0x008C INTC_PSR76_79 INTC priority select register 76 79 R W 0x0000_0000 10 3 2 9 10 16 0x0090 INTC_PSR80_83 INTC priority select register...

Page 1307: ..._PSR200_203 INTC priority select register 200 203 R W 0x0000_0000 10 3 2 9 10 16 0x010C INTC_PSR204_207 INTC priority select register 204 207 R W 0x0000_0000 10 3 2 9 10 16 0x0110 INTC_PSR208_211 INTC...

Page 1308: ...1 INTC priority select register 308 311 R W 0x0000_0000 10 3 2 9 10 16 0x0178 INTC_PSR312_315 INTC priority select register 312 315 R W 0x0000_0000 10 3 2 9 10 16 0x017A 0x3FFF Reserved 0xFFF4_C000 FE...

Page 1309: ...21 25 27 0x0154 0x017F Reserved 0x0180 ERDSR Pointer to receive descriptor ring R W 3 25 3 4 22 25 27 0x0184 ETDSR Transmit buffer descriptor ring start register R W 3 25 3 4 23 25 28 0x0188 EMRBR Rec...

Page 1310: ...er 0 R W1 0x0FFF_0000 34 3 2 18 34 21 0x0064 THRHLR1 Threshold register 1 R W1 0x0FFF_0000 34 3 2 18 34 21 0x0068 THRHLR2 Threshold register 2 R W1 0x0FFF_0000 34 3 2 18 34 21 0x006C THRHLR3 Threshold...

Page 1311: ...9 data register R 0x0000_0000 34 3 2 35 34 39 0x0128 PRECDATAREG10 Channel 10 data register R 0x0000_0000 34 3 2 35 34 39 0x012C PRECDATAREG11 Channel 11 data register R 0x0000_0000 34 3 2 35 34 39 0x...

Page 1312: ...4 39 0x01A4 INTDATAREG9 Channel 41 data register R 0x0000_0000 34 3 2 36 34 39 0x01A8 INTDATAREG10 Channel 42 data register R 0x0000_0000 34 3 2 36 34 39 0x01AC INTDATAREG11 Channel 43 data register R...

Page 1313: ...r R 0x0000_0000 34 3 2 37 34 40 0x0224 EXTDATAREG9 Channel 73 data register R 0x0000_0000 34 3 2 37 34 40 0x0228 EXTDATAREG10 Channel 74 data register R 0x0000_0000 34 3 2 37 34 40 0x022C EXTDATAREG11...

Page 1314: ...ter R W 0x80 32 3 2 3 32 8 0x0003 IBSR I2 C bus status register R W 0x80 32 3 2 4 32 9 0x0004 IBDR I2 C bus data I O register R W 0x00 32 3 2 5 32 10 0x0005 IBIC I2 C bus interrupt configuration regis...

Page 1315: ...ter R 0x0000_0000 30 3 2 7 30 21 0x003C DSPI_TXFR0 DSPI transmit FIFO register 0 R 0x0000_0000 30 3 2 8 30 21 0x0040 DSPI_TXFR1 DSPI transmit FIFO register 1 R 0x0000_0000 30 3 2 8 30 21 0x0044 DSPI_T...

Page 1316: ...t FIFO register 2 R 0x0000_0000 30 3 2 8 30 21 0x0048 DSPI_TXFR3 DSPI transmit FIFO register 3 R 0x0000_0000 30 3 2 8 30 21 0x004C 0x0078 Reserved 0x007C DSPI_RXFR0 DSPI receive FIFO register 0 R 0x00...

Page 1317: ...2 6 31 12 0x000C eSCI_LCR1 eSCI LIN control register 1 R W 0x0000 31 3 2 7 31 13 0x000E eSCI_LCR2 eSCI LIN control register 2 R W 0x0000 31 3 2 8 31 15 0x00010 eSCI_LTR eSCI LIN transmit register R W...

Page 1318: ...8 eSCI_IFSR1 eSCI interrupt flag and status register 1 R W 0x0000 31 3 2 5 31 11 0x000A eSCI_IFSR2 eSCI interrupt flag and status register 2 R W 0x0000 31 3 2 6 31 12 0x000C eSCI_LCR1 eSCI LIN control...

Page 1319: ...000 31 3 2 2 31 6 0x0004 eSCI_CR2 eSCI control register 2 R W 0x0200 31 3 2 3 31 8 0x0006 eSCI_SDR eSCI data register R W 0x0000 31 3 2 4 31 10 0x0008 eSCI_IFSR1 eSCI interrupt flag and status registe...

Page 1320: ...ation Interface eSCI 0x0000 eSCI_BRR eSCI baud rate register R W 0x0004 31 3 2 1 31 6 0x0002 eSCI_CR1 eSCI control register 1 R W 0x0000 31 3 2 2 31 6 0x0004 eSCI_CR2 eSCI control register 2 R W 0x020...

Page 1321: ...pt flags 1 R W 0x0000_0000 29 3 4 10 29 25 0x0034 0x007F Reserved 0x0080 MB0 Message buffer 0 R W 0x0000_0000 29 3 2 29 7 0x0090 MB1 Message buffer 1 R W 0x0000_0000 29 3 2 29 7 0x00AO MB2 Message buf...

Page 1322: ...x0000_0000 29 3 2 29 7 0x0270 MB31 Message buffer 31 R W 0x0000_0000 29 3 2 29 7 0x0280 MB32 Message buffer 32 R W 0x0000_0000 29 3 2 29 7 0x0290 MB33 Message buffer 33 R W 0x0000_0000 29 3 2 29 7 0x0...

Page 1323: ...00_0000 29 3 4 11 29 26 0x0884 CANA_RXIMR1 Rx individual mask register 1 R W 0x0000_0000 29 3 4 11 29 26 0x0888 CANA_RXIMR2 Rx individual mask register 2 R W 0x0000_0000 29 3 4 11 29 26 0x088C CANA_RX...

Page 1324: ...08F8 CANA_RXIMR30 Rx individual mask register 30 R W 0x0000_0000 29 3 4 11 29 26 0x08FC CANA_RXIMR31 Rx individual mask register 31 R W 0x0000_0000 29 3 4 11 29 26 0x0900 CANA_RXIMR32 Rx individual ma...

Page 1325: ...26 0x096C CANA_RXIMR59 Rx individual mask register 59 R W 0x0000_0000 29 3 4 11 29 26 0x0970 CANA_RXIMR60 Rx individual mask register 60 R W 0x0000_0000 29 3 4 11 29 26 0x0974 CANA_RXIMR61 Rx individu...

Page 1326: ...9 3 2 29 7 0x0130 MB11 Message buffer 11 R W 0x0000_0000 29 3 2 29 7 0x0140 MB12 Message buffer 12 R W 0x0000_0000 29 3 2 29 7 0x0150 MB13 Message buffer 13 R W 0x0000_0000 29 3 2 29 7 0x0160 MB14 Mes...

Page 1327: ...x0000_0000 29 3 2 29 7 0x0330 MB43 Message buffer 43 R W 0x0000_0000 29 3 2 29 7 0x0340 MB44 Message buffer 44 R W 0x0000_0000 29 3 2 29 7 0x0350 MB45 Message buffer 45 R W 0x0000_0000 29 3 2 29 7 0x0...

Page 1328: ...B_RXIMR11 Rx individual mask register 11 R W 0x0000_0000 29 3 4 11 29 26 0x08B0 CANB_RXIMR12 Rx individual mask register 12 R W 0x0000_0000 29 3 4 11 29 26 0x08B4 CANB_RXIMR13 Rx individual mask regis...

Page 1329: ...0928 CANB_RXIMR42 Rx individual mask register 42 R W 0x0000_0000 29 3 4 11 29 26 0x092C CANB_RXIMR43 Rx individual mask register 43 R W 0x0000_0000 29 3 4 11 29 26 0x0930 CANB_RXIMR44 Rx individual ma...

Page 1330: ...ask R W 0xFFFF_FFFF 29 3 4 4 2 29 1 9 0x0018 CANC_RX15MASK Rx buffer 15 mask R W 0xFFFF_FFFF 29 3 4 4 3 29 1 9 0x001C CANC_ECR Error counter register R W 0x0000_0000 29 3 2 29 7 0x0020 CANC_ESR Error...

Page 1331: ...000_0000 29 3 2 29 7 0x01F0 MB23 Message buffer 23 R W 0x0000_0000 29 3 2 29 7 0x0200 MB24 Message buffer 24 R W 0x0000_0000 29 3 2 29 7 0x0210 MB25 Message buffer 25 R W 0x0000_0000 29 3 2 29 7 0x022...

Page 1332: ...0_0000 29 3 2 29 7 0x0400 MB56 Message buffer 56 R W 0x0000_0000 29 3 2 29 7 0x0410 MB57 Message buffer 57 R W 0x0000_0000 29 3 2 29 7 0x0420 MB58 Message buffer 58 R W 0x0000_0000 29 3 2 29 7 0x0430...

Page 1333: ...8 CANC_RXIMR22 Rx individual mask register 22 R W 0x0000_0000 29 3 4 11 29 26 0x08DC CANC_RXIMR23 Rx individual mask register 23 R W 0x0000_0000 29 3 4 11 29 26 0x08E0 CANC_RXIMR24 Rx individual mask...

Page 1334: ...mask register 52 R W 0x0000_0000 29 3 4 11 29 26 0x0954 CANC_RXIMR53 Rx individual mask register 53 R W 0x0000_0000 29 3 4 11 29 26 0x0958 CANC_RXIMR54 Rx individual mask register 54 R W 0x0000_0000 2...

Page 1335: ...29 7 0x00B0 MB3 Message buffer 3 R W 0x0000_0000 29 3 2 29 7 0x00C0 MB4 Message buffer 4 R W 0x0000_0000 29 3 2 29 7 0x00D0 MB5 Message buffer 5 R W 0x0000_0000 29 3 2 29 7 0x00E0 MB6 Message buffer 6...

Page 1336: ...x0000_0000 29 3 2 29 7 0x02B0 MB35 Message buffer 35 R W 0x0000_0000 29 3 2 29 7 0x02C0 MB36 Message buffer 36 R W 0x0000_0000 29 3 2 29 7 0x02D0 MB37 Message buffer 37 R W 0x0000_0000 29 3 2 29 7 0x0...

Page 1337: ...MR4 Rx individual mask register 4 R W 0x0000_0000 29 3 4 11 29 26 0x0894 CAND_RXIMR5 Rx individual mask register 5 R W 0x0000_0000 29 3 4 11 29 26 0x0898 CAND_RXIMR6 Rx individual mask register 6 R W...

Page 1338: ...0908 CAND_RXIMR34 Rx individual mask register 34 R W 0x0000_0000 29 3 4 11 29 26 0x090C CAND_RXIMR35 Rx individual mask register 35 R W 0x0000_0000 29 3 4 11 29 26 0x0910 CAND_RXIMR36 Rx individual ma...

Page 1339: ...idual mask register 62 R W 0x0000_0000 29 3 4 11 29 26 0x097C CAND_RXIMR63 Rx individual mask register 63 R W 0x0000_0000 29 3 4 11 29 26 0x0980 0x3FFF Reserved 0xFFFD_0000 FlexCAN_E Chapter 29 Contro...

Page 1340: ...29 3 2 29 7 0x0170 MB15 Message buffer 15 R W 0x0000_0000 29 3 2 29 7 0x0180 MB16 Message buffer 16 R W 0x0000_0000 29 3 2 29 7 0x0190 MB17 Message buffer 17 R W 0x0000_0000 29 3 2 29 7 0x01A0 MB18 M...

Page 1341: ...x0000_0000 29 3 2 29 7 0x0370 MB47 Message buffer 47 R W 0x0000_0000 29 3 2 29 7 0x0380 MB48 Message buffer 48 R W 0x0000_0000 29 3 2 29 7 0x0390 MB49 Message buffer 49 R W 0x0000_0000 29 3 2 29 7 0x0...

Page 1342: ...ster 14 R W 0x0000_0000 29 3 4 11 29 26 0x08BC CANE_RXIMR15 Rx individual mask register 15 R W 0x0000_0000 29 3 4 11 29 26 0x08C0 CANE_RXIMR16 Rx individual mask register 16 R W 0x0000_0000 29 3 4 11...

Page 1343: ...0938 CANE_RXIMR46 Rx individual mask register 46 R W 0x0000_0000 29 3 4 11 29 26 0x093C CANE_RXIMR47 Rx individual mask register 47 R W 0x0000_0000 29 3 4 11 29 26 0x0940 CANE_RXIMR48 Rx individual ma...

Page 1344: ...masks 2 R W 0x0000_0000 29 3 4 7 29 23 0x0028 CANF_IMASK1 Interrupt masks 1 R W 0x0000_0000 29 3 4 8 29 24 0x002C CANF_IFLAG2 Interrupt flags 2 R W 0x0000_0000 29 3 4 9 29 24 0x0030 CANF_IFLAG1 Interr...

Page 1345: ...x0000_0000 29 3 2 29 7 0x0230 MB27 Message buffer 27 R W 0x0000_0000 29 3 2 29 7 0x0240 MB28 Message buffer 28 R W 0x0000_0000 29 3 2 29 7 0x0250 MB29 Message buffer 29 R W 0x0000_0000 29 3 2 29 7 0x0...

Page 1346: ...0 R W 0x0000_0000 29 3 2 29 7 0x0450 MB61 Message buffer 61 R W 0x0000_0000 29 3 2 29 7 0x0460 MB62 Message buffer 62 R W 0x0000_0000 29 3 2 29 7 0x0470 MB63 Message buffer 63 R W 0x0000_0000 29 3 2 2...

Page 1347: ...08E8 CANF_RXIMR26 Rx individual mask register 26 R W 0x0000_0000 29 3 4 11 29 26 0x08EC CANF_RXIMR27 Rx individual mask register 27 R W 0x0000_0000 29 3 4 11 29 26 0x08F0 CANF_RXIMR28 Rx individual ma...

Page 1348: ...dividual mask register 56 R W 0x0000_0000 29 3 4 11 29 26 0x0964 CANF_RXIMR57 Rx individual mask register 57 R W 0x0000_0000 29 3 4 11 29 26 0x0968 CANF_RXIMR58 Rx individual mask register 58 R W 0x00...

Page 1349: ...tion register 11 R W 0x0000_0000 33 4 1 4 33 6 0x0060 CTU_EVTCFGR12 Event configuration register 12 R W 0x0000_0000 33 4 1 4 33 6 0x0064 CTU_EVTCFGR13 Event configuration register 13 R W 0x0000_0000 3...

Page 1350: ...0007 CHCONFIG7 Channel 7 configuration R W 0x00 23 3 2 1 23 4 0x0008 CHCONFIG8 Channel 8 configuration R W 0x00 23 3 2 1 23 4 0x0009 CHCONFIG9 Channel 9 configuration R W 0x00 23 3 2 1 23 4 0x000A CHC...

Page 1351: ...flag register R W 0x0000_0000 22 3 2 5 22 7 0x0110 LDVAL2 Timer 2 load value register R W 0x0000_0000 22 3 2 2 22 5 0x0114 CVAL2 Timer 2 current value register R W 0x0000_0000 22 3 2 3 22 5 0x0118 TC...

Page 1352: ...anced Modular Input Output Subsystem eMIOS200 0x0000 EMIOS_MCR Module configuration register R W 0x0000_0000 28 3 2 1 28 9 0x0004 EMIOS_GFR Global flag register R 0x0000_0000 28 3 2 2 28 10 0x0008 EMI...

Page 1353: ...0x0000_0000 28 3 2 9 28 19 0x0094 EMIOS_ALTA 3 Alternate A register R W 0x0000_0000 28 3 2 10 28 19 0x0098 0x009F Reserved 0x00A0 EMIOS_CADR 4 Channel A data register R W 0x0000_0000 28 3 2 5 28 12 0...

Page 1354: ...0 28 3 2 6 28 12 0x0126 EMIOS_CCNTR 8 Counter register R 0x0000_0000 28 3 2 7 28 13 0x012C EMIOS_CCR 8 Control register R W 0x0000_0000 28 3 2 8 28 14 0x0130 EMIOS_CSR 8 Status register R 0x0000_0000...

Page 1355: ...W 0x0000_0000 28 3 2 10 28 19 0x01B8 0x01BF Reserved 0x01C0 EMIOS_CADR 13 Channel A data register R W 0x0000_0000 28 3 2 5 28 12 0x01C4 EMIOS_CBDR 13 Channel B data register R W 0x0000_0000 28 3 2 6...

Page 1356: ...3 2 7 28 13 0x024C EMIOS_CCR 17 Control register R W 0x0000_0000 28 3 2 8 28 14 0x0250 EMIOS_CSR 17 Status register R 0x0000_0000 28 3 2 9 28 19 0x0254 EMIOS_ALTA 17 Alternate A register R W 0x0000_00...

Page 1357: ...22 Channel A data register R W 0x0000_0000 28 3 2 5 28 12 0x02E4 EMIOS_CBDR 22 Channel B data register R W 0x0000_0000 28 3 2 6 28 12 0x02E8 EMIOS_CCNTR 22 Counter register R 0x0000_0000 28 3 2 7 28...

Page 1358: ...ter R W 0x0000_0000 28 3 2 8 28 14 0x0370 EMIOS_CSR 26 Status register R 0x0000_0000 28 3 2 9 28 19 0x0374 EMIOS_ALTA 26 Alternate A register R W 0x0000_0000 28 3 2 10 28 19 0x0378 0x037F Reserved 0x0...

Page 1359: ...d 0x0400 EMIOS_CADR 31 Channel A data register R W 0x0000_0000 28 3 2 5 28 12 0x0404 EMIOS_CBDR 31 Channel B data register R W 0x0000_0000 28 3 2 6 28 12 0x0408 EMIOS_CCNTR 31 Counter register R 0x000...

Page 1360: ...SIU_PCR9 Pad configuration register 9 PA9 R W 0x0000 8 3 2 13 8 22 0x0054 SIU_PCR10 Pad configuration register 10 PA10 R W 0x0000 8 3 2 13 8 22 0x0056 SIU_PCR11 Pad configuration register 11 PA11 R W...

Page 1361: ...8 22 0x0092 SIU_PCR41 Pad configuration register 41 PC9 R W 0x0000 8 3 2 13 8 22 0x0094 SIU_PCR42 Pad configuration register 42 PC10 R W 0x0000 8 3 2 13 8 22 0x0096 SIU_PCR43 Pad configuration regist...

Page 1362: ...8 22 0x00D2 SIU_PCR73 Pad configuration register 73 PE9 R W 0x0000 8 3 2 13 8 22 0x00D4 SIU_PCR74 Pad configuration register 74 PE10 R W 0x0000 8 3 2 13 8 22 0x00D6 SIU_PCR75 Pad configuration regist...

Page 1363: ...SIU_PCR105 Pad configuration register 105 PG9 R W 0x0000 8 3 2 13 8 22 0x0114 SIU_PCR106 Pad configuration register 106 PG10 R W 0x0000 8 3 2 13 8 22 0x0116 SIU_PCR107 Pad configuration register 107 P...

Page 1364: ...22 0x0152 SIU_PCR137 Pad configuration register 137 PJ9 R W 0x0000 8 3 2 13 8 22 0x0154 SIU_PCR138 Pad configuration register 138 PJ10 R W 0x0000 8 3 2 13 8 22 0x0156 SIU_PCR139 Pad configuration reg...

Page 1365: ...W 0x0000_0000 8 3 2 14 8 26 0x0648 SIU_GPDO72_75 GPIO pin data output register 72 75 R W 0x0000_0000 8 3 2 14 8 26 0x064C SIU_GPDO76_79 GPIO pin data output register 76 79 R W 0x0000_0000 8 3 2 14 8 2...

Page 1366: ...data input register 36 39 R W 0x0U0U_0U0U 8 3 2 15 8 28 0x0828 SIU_GPDI40_43 GPIO pin data input register 40 43 R W 0x0U0U_0U0U 8 3 2 15 8 28 0x082C SIU_GPDI44_47 GPIO pin data input register 44 47 R...

Page 1367: ...8 0x0898 SIU_GPDI152_154 GPIO pin data input register 152 154 R W 0x0U0U_0U0U 8 3 2 15 8 28 0x089C 0x0903 Reserved 0x0904 SIU_ISEL1 IMUX select register 1 R W 0x0000_0000 8 3 2 16 8 29 0x0908 SIU_ISEL...

Page 1368: ...R W 3 8 3 2 36 8 52 0x0C54 0x0C83 Reserved 0x0C84 SIU_MPGPDO1 Masked parallel GPIO data output register 1 R 0x0000_0000 8 3 2 37 8 52 0x0C88 SIU_MPGPDO2 Masked parallel GPIO data output register 2 R 0...

Page 1369: ...I_D R W 0x0000_0000 8 3 2 60 8 66 0x0D78 0x0D7B SIU_DSPIDHLD SIU_DSPIDH L select register for DSPI_D R W 0x0000_0000 8 3 2 61 8 67 0x0D7C 0x3FFF Reserved 0xFFFE_C000 CRP Chapter 6 Clocks Reset and Pow...

Page 1370: ...x000C SLL Secondary low mid address space block locking register R W 0x0013_03FF 12 3 2 4 12 13 0x0010 LMS Low mid address space block select register R W 0x0000_0000 12 3 2 5 12 14 0x0014 HBS High ad...

Page 1371: ...3 1 9 3 1 In this column R W indicates a read write register R indicates a read only register and W indicates a write only register Note that R W registers may contain some read only or write only bit...

Page 1372: ...572 DEAR Data Exception Address Register 61 IVPR Interrupt Vector Prefix Register 63 IVOR1 Interrupt Vector Offset Register 1 401 IVOR2 Interrupt Vector Offset Register 2 402 IVOR3 Interrupt Vector Of...

Page 1373: ...r 336 DEC Decrementer Register 22 DECAR Decrementer Auto reload Register 54 Debug Registers DBCR0 Debug Control Register 0 308 DBCR1 Debug Control Register 1 309 DBCR2 Debug Control Register 2 310 DBC...

Page 1374: ...gister 0 1016 APU Registers SPEFSCR SPE APU Status and Control Register 512 Table A 6 e200z6 Core SPR Numbers User Mode Register Description SPR decimal General Registers CTR Count Register 9 LR Link...

Page 1375: ...Microcontroller Reference Manual Rev 1 Freescale Semiconductor A 117 APU Registers SPEFSCR SPE APU Status and Control Register 512 Table A 6 e200z6 Core SPR Numbers User Mode continued Register Descri...

Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...

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