NXP Semiconductors PXN2020, Reference Manual, Page: 635 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-21
This register provides the means to control some of the interrupt request lines and provides the
corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a
binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these
flags is depicted in
Figure 26-150 . For more details on interrupt generation, see Section 26.6.20, Interrupt
Support. These flags are cleared automatically when all of the corresponding interrupt flags or interrupt
enables in the related interrupt flag and enable registers are cleared by the application.
Table 26-16. GIFER Field Descriptions
Field Description
MIF Module Interrupt Flag — This flag is set if at least one of the other interrupt flags is in this register is asserted
and the related interrupt enable is asserted, too. The controller generates the module interrupt request if MIE is
asserted.
0 No interrupt flag is asserted or no interrupt enable is set.
1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too.
PRIF Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the Protocol
Interrupt Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1) is asserted and the related
interrupt enable flag is asserted, too. The controller generates the combined protocol interrupt request if the
PRIE flag is asserted.
0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set.
1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1.
CHIF CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register
(CHIERFR) is asserted and the chi error interrupt enable GIFER[CHIE] is asserted. The controller generates the
combined CHI error interrupt if the CHIE flag is asserted, too.
0 All CHI error flags are equal to 0 or the chi error interrupt is disabled.
1 At least one CHI error flag is asserted and chi error interrupt is enabled.
WUPIF Wakeup Interrupt Flag — This flag is set when the controller has received a wakeup symbol on the FlexRay
bus. The application can determine on which channel the wakeup symbol was received by reading the related
wakeup flags WUB and WUA in the
Protocol Status Register 3 (PSR3). The controller generates the wakeup
interrupt request if the WUPIE flag is asserted.
0 No wakeup condition or interrupt disabled.
1 Wakeup symbol received on FlexRay bus and interrupt enabled.
FAFBIF Receive FIFO Channel B Almost Full Interrupt Flag — This flag is set when one of the following events occurs
a) the current number of FIFO B entries is equal to or greater than the watermark defined by the WM field in the
Receive FIFO Watermark and Selection Register (RFWMSR) , and the controller writes a received message into
the FIFO B, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by Receive FIFO Periodic
Timer Register (RFPTR) expires.
0 No such event.
1 FIFO B almost full event has occurred.
FAFAIF Receive FIFO Channel A Almost Full Interrupt Flag — This flag is set when one of the following events occurs
a) the current number of FIFO A entries is equal to or greater than the watermark defined by the WM field in the
Receive FIFO Watermark and Selection Register (RFWMSR) , and the controller writes a received message into
the FIFO A, or
b) the current number of FIFO B entries is at least 1 and the periodic timer as defined by Receive FIFO Periodic
Timer Register (RFPTR) expires.
0 No such event.
1 FIFO A almost full event has occurred.