NXP Semiconductors PXN2020, Reference Manual, Page: 272 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-4 Freescale Semiconductor
Figure 10-2. INTC Software Vector Mode
Typical program flow for software vector mode is shown in Figure 10-3 .
Figure 10-3. Program Flow–Software Vector Mode
The common interrupt exception handler address is calculated by hardware as shown in Figure 10-4 for
the Z0 core and Figure 10-5 for the Z6 core. The upper half of the interrupt vector prefix register (IVPR)
is added to the offset contained in the external input interrupt vector offset register (IVOR4).
NOTE
Since bits IVOR4[28:31] are not part of the offset value for the Z6, the
vector offset must be located on a quad-word (16-byte) aligned location in
memory. For the Z0 core, the value of IVOR4 is hard coded to 0x040.
IRQs
Interrupt
controller
(INTC)
External interrupt
exception request
e200z6
or
e200z0
core
ISR ISR 0 address ISR 0
ISR ISR 1
•
•
•
ISR ISR n
•
•
•
ISR ISR N – 1
ISR n address
ISR N – 1 address
ISR 1 address
•
•
•
•
•
•
Prolog
(Including
using IACKR
to get vector
then bl ISR_n
Epilog
IVPR + IVOR4
IRQ[n]
taken
IACKR
Instructions Address Instructions Address
VTBA
N is the maximum number of usable interrupt vectors, which equals 316, and includes 26 reserved IRQ vectors
and eight software-settable IRQ vectors.