NXP Semiconductors PXN2020, Reference Manual, Page: 275 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-7
Figure 10-7. Z0 Hardware Vector Mode: Interrupt Exception Handler Address Calculation
Figure 10-8. Z6 Hardware Vector Mode: Interrupt Exception Handler Address Calculation
The processor negates INTC’s interrupt request when automatically acknowledging the interrupt request.
However, the interrupt request to the processor do not negate if a higher priority interrupt request arrives.
Even in this case, the interrupt vector number does not update to the higher priority request until the lower
priority request is acknowledged by the processor.
The assertion of the interrupt acknowledge signal pushes the PRI value in the INTC_CPR_PRC n onto the
LIFO and updates PRI in the INTC_CPR_PRC n with the new priority.
10.2 External Signal Description
The INTC has no direct external MCU signals. However, there are external pins that can be configured in
the SIU as external interrupt request input pins. When configured in this function, an interrupt on the pin
sets an external interrupt flag. These flags can cause one of five peripheral interrupt requests to the
interrupt controller.
For more information on external interrupts, the pins used, and how to configure them, refer to Chapter 3,
Signal Description, and Chapter 8, System Integration Unit (SIU), for more information on these pins.
+
=
IVPR
0 19 20 31
Vector base 0x000
Hardware Vector Mode Offset
0 19 20 21 29 30 31
0x0_0000 0b1 Vector 0b00
Hardware Vector Mode Interrupt Exception Handler Address
0 19 20 21 29 30 31
Vector base 0b1 Vector 0b00
31 16 15 0
IVPR
31 28 27 16 15 0 0
+ Hardware vector
15 0
0b0000 INTC_IACKR[INTVEC]
PREFIX
0x0000
PREFIX
18
0b000
19
0x0000
31 28 27 16
0b0000 IRQ SPECIFIC OFFSET
18
0b000
19 16
= Interrupt exception
handler address
mode offset