NXP Semiconductors PXN2020, Reference Manual, Page: 974 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-48 Freescale Semiconductor
every odd-numbered SCK edge. The slave also places new data on the slave SOUT on every
odd-numbered clock edge.
The master places its second data bit on the SOUT line one system clock after odd-numbered SCK edge.
The point where the master samples the slave SOUT is selected by writing to the SMPL_PT field in the
DSPI_MCR.
Table 30-33 lists the number of system clock cycles between the active edge of SCK and the
master sample point. The master sample point can be delayed by one or two system clock cycles.
Figure 30-31 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed master sample points are indicated with a lighter shaded arrow.
Figure 30-31. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4)
30.4.8.4 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1)
Figure 30-32 shows the modified transfer format for CPHA = 1. Only the condition where CPOL = 0 is
described. At the start of a transfer, the DSPI asserts the PCS signal to the slave device. After the PCS to
SCK delay has elapsed, the master and the slave put data on their SOUT pins at the first edge of SCK. The
slave samples the master SOUT signal on the even-numbered edges of SCK. The master samples the slave
SOUT signal on the odd-numbered SCK edges starting with the third SCK edge. The slave samples the
Table 30-33. Delayed Master Sample Point
SMPL_PT
Number of System Clock Cycles Between
Odd-Numbered Edge of SCK and Sampling of SIN
00 0
01 1
10 2
11 Reserved
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
System clock
1 2 3 4 5 6
PCS
x
t
ASC
SCK
Master Sample
Slave SOUT
Master SOUT
System clock
System clock
Slave Sample
t
CSC