NXP Semiconductors PXN2020, Reference Manual, Page: 218 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-36 Freescale Semiconductor
8.3.2.19 Chip Configuration Register (SIU_CCR)
Offset: SI 0x0980 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH DISNEX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
TEST
LOCK
0 0 0 0 0 0
1
0
2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Writes to this bit have no effect, but reads return the written value.
2
Reserved, do not write.
Figure 8-22. Chip Configuration Register (SIU_CCR)
Table 8-24. SIU_CCR Field Descriptions
Field Description
MATCH Compare Register Match. The MATCH bit is a read-only bit that holds the value of the match input signal to the
SIU. The match input is asserted if the serial boot password provided by the user matches the password stored
in the flash.
0 Match input signal is negated.
1 Match input signal is asserted.
DISNEX Disable Nexus. The DISNEX bit is a read-only bit that holds the value of the Nexus disable input signal to the SIU.
When system reset negates, the value in this bit depends on the censorship control word and the boot
configuration bits.
0 Nexus disable input signal negated.
1 Nexus disable input signal asserted.
TESTLOCK TEST Lock. The TESTLOCK bit prevents access to Freescale internal test features.
These internal test features are enabled by writing to reserved test bits in the device. Setting the TESTLOCK bit
locks the test bits so that they cannot be changed inadvertently by runaway code.
Customer initialization code should always set this bit.
0 Internal test features could be enabled.
1 Internal test features are disabled.