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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-80
Freescale Semiconductor
Each individual message buffer consists of two parts, the physical message buffer, which is located in the
FlexRay memory, and the message buffer control data, which are located in dedicated registers. The
structure of an individual message buffer is given in
.
Each individual message buffer has a message buffer number
n
assigned, which determines the set of
message buffer control registers associated to this individual message buffer. The individual message
buffer with message buffer number
n
is controlled by the registers MBCCSR
n
, MBCCFR
n
, MBFIDR
n
,
and MBIDXR
n
.
The connection between the message buffer control registers and the physical message buffer is
established by the message buffer index field MBIDX in the
Message Buffer Index Registers (MBIDXRn)
.
The start address SADR_MBHF of the related message buffer header field in the FlexRay memory is
determined according to
SADR_MBHF = (MBIDXRn[MBIDX] * 10) + SMBA
Eqn. 26-3
Figure 26-104. Individual Message Buffer Structure
26.6.3.1.1
Individual Message Buffer Segments
The set of the individual message buffers can be split up into two message buffer segments using the
Message Buffer Segment Size and Utilization Register (MBSSUTR)
. All individual message buffers with
a message buffer number
n
< MBSSUTR[LAST_MB_SEG1] belong to the first message buffer segment.
All individual message buffers with a message buffer number
n
> MBSSUTR[LAST_MB_SEG1] belong
to the second message buffer segment. The following rules apply to the length of the message buffer data
field:
•
all physical message buffers associated to individual message buffers that belong to the same
message buffer segment must have message buffer data fields of the same length
•
the minimum length of the message buffer data field for individual message buffers in the first
message buffer segment is 2 * MBDSR[MBSEG1DS] bytes
•
the minimum length of the message buffer data field for individual message buffers assigned to the
second segment is 2 * MBDSR[MBSEG2DS] bytes.
MBFIDRn
Message Buffer Control Registers
MBCCSRn
MBCCFRn
MBIDXRn
(min) MBDSR[MBSEG1DS] * 2 bytes / MBDSR[MBSEG2DS] * 2 bytes
Data Field Offset
Frame Data
Message Buffer Header Field
Message Buffer Data Field
Slot Status
Frame Header
SADR_MBDF
SADR_MBHF
Fl
e
x
Ra
y Memor
y
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...