NXP Semiconductors PXN2020, Reference Manual, Page: 276 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-8 Freescale Semiconductor
10.3 Memory Map and Registers
10.3.1 INTC Memory Map
Table 10-1 shows the INTC memory map.
NOTE
To ensure compatibility with all PowerPC processors, the TLB entry
covering the INTC memory map must be configured as guarded, both in
software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read
speculatively.
Table 10-1. INTC Memory Map
Offset from
INTC_BASE_ADDR
(0xFFF4_8000)
Register Access
Reset
Value
Section/Page
0x0000 INTC_MCR—INTC module configuration register R/W 0x0000_0000 10.3.2.1/10-9
0x0004 Reserved
0x0008 INTC_CPR_PRC0—INTC current priority register for
processor 0 (Z6) R/W 0x0000_000F 10.3.2.2/10-10
0x00C INTC_CPR_PRC1—INTC current priority register for
processor 1 (Z0) R/W 0x0000_000F 10.3.2.3/10-12
0x0010 INTC_IACKR_PRC0—INTC interrupt acknowledge register
for processor 0 (Z6) R
1
/W
1
When the HVEN bit in the INTC module configuration register (INTC_MCR) is asserted, a read of the INTC_IACKR_PRCn has
no side effects.
0x0000_0000 10.3.2.4/10-12
0x0014 INTC_IACKR_PRC1—INTC interrupt acknowledge register
for processor 1 (Z0) R
1
/W 0x0000_0000 10.3.2.5/10-14
0x0018 INTC_EOIR_PRC0—INTC end of interrupt register for
processor 0 (Z6) W 0x0000_0000 10.3.2.6/10-14
0x001C INTC_EOIR_PRC1—INTC end of interrupt register for
processor 1 (Z0) W 0x0000_0000 10.3.2.7/10-15
0x0020 INTC_SSCIR0_3—INTC software set/clear interrupt register
0–3 R/W 0x0000_0000 10.3.2.8/10-15
0x0024 INTC_SSCIR4_7—INTC software set/clear interrupt register
4–7 R/W 0x0000_0000 10.3.2.8/10-15
0x0028 – 0x003F Reserved
0x0040 – 0x017B
2
2
A complete list of address offsets for INTC_PSR is provided in Table 10-10 and in Table A-4 .
INTC_PSR0_3—INTC priority select register 0 – 3 to
INTC_PSR312_315 — INTC priority select register 312 – 315 R/W 0x0000_0000 10.3.2.9/10-16
0x017C – 0x3FFF Reserved