NXP Semiconductors PXN2020, Reference Manual, Page: 277 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-9
• In hardware vector mode, guarded writes to the INTC_CPR or
INTC_EOIR complete before the interrupt acknowledge signal from the
processor asserts.
10.3.2 Register Descriptions
With the exception of the INTC_SSCI n and INTC_PSR n registers, all registers are 32 bits in width. Any
combination of accessing the four bytes of a register with a single access is supported, provided that the
access does not cross a register boundary. These supported accesses include types and sizes of eight bits,
aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits.Although INTC_SSCI
n and
INTC_PSR n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the
access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR_PRC0 and INTC_IACR_PRC1 are
the same regardless of the size of the read. In either software or hardware vector mode, the size of a write
to either INTC_EOIR_PRC0 or INTC_EOIR_PRC1 does not affect the operation of the write.
10.3.2.1 INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
Offset: INTC_BAS 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
VTES_
PRC1
0 0 0 0
HVEN_
PRC1
0 0
VTES_
PRC0
0 0 0 0
HVEN_
PRC0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-9. INTC Module Configuration Register (INTC_MCR)
Table 10-2. INTC_MCR Field Descriptions
Field Description
VTES_PRC1 For software mode only, the Vector Table Entry Size for Processor 1 (Z0). The VTES_PRC1 bit controls the
number of 0s to the right of INTVEC_PRC1 in INTC_IACKR_PRC1. If the contents of INTC_IACKR_PRC1
are used as an address of an entry in a vector table, then the number of rightmost 0s will determine the size
of each vector table entry.
0 4 bytes.
1 8 bytes.
HVEN_PRC1 Hardware Vector Enable for Processor 1 (Z0). The HVEN bit controls whether the INTC is in hardware vector
mode or software vector mode. Refer to
Section 10.1.3, Modes of Operation, for details of handshaking with
the processor in each mode.
0 Software vector mode.
1 Hardware vector mode.