NXP Semiconductors PXN2020, Reference Manual, Page: 313 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-45
of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher
priority portion, to set a SET
n bit in INTC software set/clear interrupt registers
(INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SET n causes a software settable interrupt request. This
software settable interrupt request usually has a lower PRI n value in the INTC_PSR n , and therefore does
not cause preemptive scheduling inefficiencies.
After generating a software settable interrupt request, the higher priority ISR completes. The lower priority
ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the
completion of the lower priority ISR.
10.5.7.2 Scheduling an ISR on Another Processor
Since the SET n bits in the INTC_SSCIR n are memory mapped, processors in multiple-processor systems
can schedule ISRs on the other processors. One application is that one processor wants to command
another processor to perform a piece of work and the initiating processor does not need to use the results
of that work. If the initiating processor is concerned that the processor executing the software settable ISR
has not completed the work before asking it to again execute the ISR, it can check if the corresponding
CLR
n bit in INTC_SSCIR n is asserted before again writing a 1 to the SET n bit.
Another application is the sharing of a block of data. For example, a first processor has completed
accessing a block of data and wants a second processor to then access it. Furthermore, after the second
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. The procedure is that the first processor writes a 1
to a SET
n bit on the second processor. The second processor, after accessing the block of data, clears the
corresponding CLR n bit and then writes 1 to a SET n bit on the first processor, informing it that it now can
access the block of data.
10.5.8 Lowering Priority Within an ISR
In implementations without the software-settable interrupt requests in the INTC software set/clear
interrupt registers (INTC_SSCIR0–INTC_SSCIR7), one way — besides scheduling a task through an
RTOS — to prevent preemptive scheduling inefficiencies with an ISR whose work spans multiple
priorities is to lower the current priority (see
Section 10.5.7.1, Scheduling a Lower Priority Portion of an
ISR) . However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in either INTC_CPR_PRC0 or INTC_CPR_PRC1
within an ISR to below the ISR’s corresponding PRI value in
INTC_PSR0–INTC_PSR315 allows more preemptions than the LIFO
depth can support.
Therefore, through its use of the LIFO, the INTC does not support lowering the current priority within an
ISR as a way to avoid preemptive scheduling inefficiencies.