NXP Semiconductors PXN2020, Reference Manual, Page: 375 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-11
• Processor control registers
— Machine state register (MSR). The MSR defines the state of the processor. The MSR can be
modified by the move to machine state register ( mtmsr ), system call ( sc) , and return from
exception ( rfi, rfci, rfdi) instructions. It can be read by the move from machine state register
( mfmsr) instruction. When an interrupt occurs, the contents of the MSR are saved to one of the
machine state save/restore registers (SRR1, CSRR1, DSRR1).
— Processor version register (PVR). This register is a read-only register that identifies the version
(model) and revision level of the processor built on the Power Architecture.
— Processor identification register (PIR). This read-only register is provided to distinguish the
processor from other processors in the system.
• Storage control register
— Process ID register (PID, also referred to as PID0). This register is provided to indicate the
current process or task identifier. It is used by the MMU as an extension to the effective address,
and by external Nexus 2/3/4 modules for ownership trace message generation. The Power
Architecture embedded category allows for multiple PIDs; e200z6 implements only one.
• Interrupt registers
— Data exception address register (DEAR). After a data storage interrupt (DSI), alignment
interrupt, or data TLB miss interrupt, the DEAR is set to the effective address (EA) generated
by the faulting instruction.
— Software-use special purpose registers (SPRGs). The SPRG0–SPRG7 registers are provided
for operating system use.
— Exception syndrome register (ESR). The ESR register provides a syndrome to differentiate
between the different kinds of exceptions which can generate the same interrupt.
— Interrupt vector prefix register (IVPR) and the interrupt vector offset registers
(IVOR1–IVOR15). These registers together provide the address of the interrupt handler for
different classes of interrupts.
— Save/restore registers (SRR0, SRR1). SRR0 holds the effective address for the instruction at
which execution resumes when an rfi instruction is executed at the end of a non-critical class
interrupt handler routine. SRR1 is used to save machine state on a non-critical interrupt, and
stores the MSR register contents. The MSR value is restored when an
rfi instruction is executed
at the end of a non-critical class interrupt handler routine.
— Critical save/restore registers (CSRR0, CSRR1). CSRR0 holds the effective address for the
instruction at which execution resumes when an rfci instruction is executed at the end of a
critical class interrupt handler routine. CSRR1 is used to save machine state on a critical
interrupt, and stores the MSR register contents. The MSR value is restored when an
rfci
instruction is executed at the end of a critical class interrupt routine.
• Debug facility registers
Table 13-1. PVR Values, and Processor Type and Version Numbers
Device Core PVR Value Type Version
PXN20 e200z6 0x8112_0000 0x11 0x2