NXP Semiconductors PXN2020, Reference Manual, Page: 225 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-43
HLTACK29 Halt acknowledge bit 29. When this bit is set, the I
2
C_A module is halted.
HLTACK31 Halt acknowledge bit 31. When this bit is set, the ADC module is halted.
Offset: SIU_HLTACK1: SI 0x09B0 Access: User read-only
0 1 2
1
3 4 5
1
6
1
7
1
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
R HLT
ACK
0
HLT
ACK
1
0
HLT
ACK
3
HLT
ACK
4
0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
1
17
1
18
1
19
1
20 21 22 23 24
1
25
1
26 27 28 29 30
1
31
1
R
0 0 0 0
HLT
ACK
20
HLT
ACK
21
HLT
ACK
22
HLT
ACK
23
0 0
HLT
ACK
26
HLT
ACK
27
HLT
ACK
28
HLT
ACK
29
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Setting the corresponding bit in SIU_HLT0 sets this bit, but has no other effect.
Figure 8-29. Halt Acknowledge Register 1 (SIU_HLTACK1)
Table 8-30. SIU_HLTACK1 Register Field Descriptions
Field Description
HLTACK0 Halt acknowledge bit 0. When this bit is set, the Z6 core is halted.
Note: This flag indicates a core-generated halt, not a halt caused by writing to SIU_HLT10[HLT0].
HLTACK1 Halt acknowledge bit 1. When this bit is set, the Z0 core is halted.
Note: This flag indicates a core-generated halt, not a halt caused by writing to SIU_HLT1[HLT1].
HLTACK3 Halt acknowledge bit 3. When this bit is set, the DMA module is halted.
HLTACK4 Halt acknowledge bit 4. When this bit is set, the NPC module is halted.
HLTACK20 Halt acknowledge bit 20. When this bit is set, the ESCI_M module is halted.
HLTACK21 Halt acknowledge bit 21. When this bit is set, the ESCI_L module is halted.
HLTACK22 Halt acknowledge bit 22. When this bit is set, the ESCI_K module is halted.
HLTACK23 Halt acknowledge bit 23. When this bit is set, the ESCI_J module is halted.
HLTACK26 Halt acknowledge bit 26. When this bit is set, the DSPI_D module is halted.
HLTACK27 Halt acknowledge bit 27. When this bit is set, the DSPI_C module is halted.
HLTACK28 Halt acknowledge bit 28. When this bit is set, the I
2
C_D module is halted.
HLTACK29 Halt acknowledge bit 29. When this bit is set, the I
2
C_C module is halted.
Table 8-29. SIU_HLTACK0 Register Field Descriptions (continued)
Field Description