NXP Semiconductors PXN2020, Reference Manual, Page: 459 / 1376

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 18-19
7. Finally, consider the use of overlapping region descriptors. Application of overlapping regions can
reduce the number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are logically summed
together (the boolean OR operator). In the following example of a dual-core system, there are four
bus masters: the two processors (CP0, CP1) and two DMA engines (eDMA, a traditional data
movement engine transferring data between RAM and peripherals, and FlexRay, a second engine
transferring data to/from the RAM only). Consider the following region descriptor assignments:
In this example, there are eight descriptors used to span nine regions in the three main spaces of
the system memory map (flash, RAM, and IPS peripheral space). Each region indicates the specific
permissions for each of the four bus masters and this definition provides an appropriate set of
shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 and 3, and 3 and 4.
The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared
data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR
of the two region descriptors. Thus, CP0 has (
rw- | r--
) = (
rw-
) permissions, while CP1 has
(
--- | r--
) = (
r--
) permission in this space. Both DMA engines are excluded from this shared
processor data region. The overlapping spaces between RGD3 and RGD4 defines another shared
data space, this one for passing data from CP1 to CP0. For this overlapping space, CP0 has (
r--
| ---
) = (
r--
) permission, while CP1 has (
rw- | r--
) = (
rw-
) permission. The
non-overlapped space of RGD4 defines a private data and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters. Finally, the
slave peripheral space mapped onto the peripheral bus is partitioned into two regions: one (RGD6)
containing the MPU’s programming model accessible only to the two processor cores, and the
remaining peripheral region (RGD7) accessible to both processors and the traditional eDMA
master.
This example is intended to show one possible application of the capabilities of the memory protection
unit in a typical system.
Region Description RGDn CP0 CP1 eDMA FlexRay
CP0 Code 0
rwx r-- -- --
Flash
CP1 Code 1
r-- rwx -- --
CP0 Data & Stack 2
rw- --- -- --
RAM
CP0

CP1 Shared Data
3
r-- r-- -- --
CP1

CP0 Shared Data
CP0 Data & Stack 4
--- rw- -- --
Shared DMA Data 5
rw- rw- rw rw
MPU 6
rw- rw- -- --
IPS
Peripherals 7
rw- rw- rw --
Figure 18-12. Overlapping Region Descriptor Example