NXP Semiconductors PXN2020, Reference Manual, Page: 1230 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-80 Freescale Semiconductor
36.7.7.4 Read/Write Access Address (RWA)
The read/write access address register provides the system bus address to be accessed when initiating a
read or a write access.
36.7.7.5 Read/Write Access Data (RWD)
The read/write access data register provides the data to/from system bus memory-mapped locations when
initiating a read or a write access.
Table 36-54 shows the proper placement of data into the RWD. The “X” in the RWD column indicate byte
lanes with valid data.
Table 36-53. Read/Write Access Status Bit Encoding
Read Action Write Action ERR DV
Read access has not completed Write access completed without error 0 0
Read access error has occurred Write access error has occurred 1 0
Read access completed without error Write access has not completed 0 1
Not allowed Not allowed 1 1
Nexus Reg: 0x9 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Read/Write Address
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-57. Read/Write Access Address Register (RWA)
Nexus Reg: 0xA Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Read/Write Data
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-58. Read/Write Access Data Register (RWD)
Table 36-54. RWD Data Placement for Transfers
Transfer Size and byte
offset
RWA[2:0 RWCS[SZ]
RWD
31:24 23:16 15:8 7:0
Byte XXX 000 — — — X
Half Word XX0 001 — — X X
Word X00 010 X X X X