NXP Semiconductors PXN2020, Reference Manual, Page: 1151 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-1
Chapter 36
Nexus Development Interface (NDI)
36.1 Introduction
NOTE
The Power PC standard is to number the register bits according to the
MSB = 0 convention. However, the Nexus standard is to number the register
bits according to the LSB = 0 convention.
Register bits in this chapter are numbered according to the Nexus standard
(LSB = 0 convention).
The PXN20 device contains multiple Nexus clients that communicate over a single IEEE

-ISTO
5001™-2003 Nexus class 3+ and 2+ combined JTAG IEEE 1149.1/auxiliary out interface. Combined, all
of the Nexus clients are referred to as the Nexus development interface (NDI). Class 3+ Nexus allows for
program, data, and ownership trace of the microcontroller execution without access to the external data
and address buses. Class 2+ Nexus allows for program and ownership trace of the microcontroller
execution without access to the external data and address buses.
Communication to the NDI is handled via the auxiliary port and the JTAG port.
• The auxiliary port is comprised of 16 output pins and 1 input pin. The output pins include 1
message clock out (MCKO) pin, 12 message data out (MDO) pins, 2 message start/end out
(MSEO) pins, and 1 event out (EVTO) pin. Event in (EVTI) is the only input pin for the auxiliary
port.
• The JTAG port consists of four inputs and one output. These pins include JTAG compliance select
(JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock
input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and
are shared with the NDI through the test access port (TAP) interface. JCOMP along with power-on
reset and the TAP state machine are used to control reset for the NDI module. Ownership of the
TAP is achieved by loading the appropriate enable instruction for the desired Nexus client in the
JTAG controller (JTAGC) when JCOMP is asserted. See
Section 36.4, Memory Map and
Registers, for the JTAGC opcodes to access the different Nexus clients.
36.2 Block Diagram
Figure 36-1 shows a functional block diagram of the NDI. Figure 36-2 shows an implementation block
diagram of the PXN20 NDI, which shows how the individual Nexus blocks are combined to form the NDI.