NXP Semiconductors PXN2020, Reference Manual, Page: 420 / 1376

Semaphores
PXN20 Microcontroller Reference Manual, Rev. 1
15-8 Freescale Semiconductor
15.3.2.5 Semaphores (Secure) Reset IRQ Notification (SEMA4_RSTNTF)
As with the case of the secure reset function and the hardware gates, it is recognized that system operation
may require a reset function to re-initialize the state of the IRQ notification logic without requiring a
system-level reset.
To support this special notification reset requirement, the semaphores module implements a secure reset
mechanism which allows an IRQ notification (or all the notifications) to be initialized by following a
specific dual-write access pattern. When successful, the specified IRQ notification state machine(s) are
reset. Using a technique similar to that required for the servicing of a software watchdog timer, the secure
Table 15-5. SEMA4_RSTGT Field Descriptions
Field Description
RSTGSM Reset Gate Finite State Machine. The reset state machine is maintained in a 2-bit, three-state implementation,
defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this
machine returns to the idle (waiting for first data pattern write) state.
11 This state encoding is never used and therefore reserved.
Reads of the SEMA4_RSTGT register return the encoded state machine value. Note the RSTGSM = 0b10 state
is valid for a single machine cycle only, so it is impossible for a read to return this value.
RSTGMS Reset Gate Bus Master. This 3-bit read-only field records the logical number of the bus master performing the
gate reset function. The reset function requires that the two consecutive writes to this register be initiated by the
same bus master to succeed. This field is updated each time a write to this register occurs.
RSTGTN Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated by the
second write.
If RSTGTN < 64, then reset the single gate defined by RSTGTN, else reset all the gates. The corresponding
secure IRQ notification state machine(s) are also reset.
RSTGDP Reset Gate Data Pattern. This write-only field is accessed with the specified data patterns on the two consecutive
writes to enable the gate reset mechanism. For the first write, RSTGDP = 0xe2 while the second write requires
RSTGDP = 0x1d.
Master Master ID
e200z6 0
e200z0 1
eDMA 2
— 3
FEC 4
MLB 5
FlexRay 6
— 7