NXP Semiconductors PXN2020, Reference Manual, Page: 200 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-18 Freescale Semiconductor
8.3.2.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
The SIU_DIRSR allows selection between a DMA or interrupt request for events on the IRQ1–IRQ0
inputs. The SIU_DIRSR selects between DMA and interrupt requests. If the corresponding bits are set in
SIU_EISR and the SIU_DIRER, then the DMA/interrupt request select bit determines whether a DMA or
interrupt request is asserted.
Offset: SI 0x0018 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIRE
15
EIRE
14
EIRE
13
EIRE
12
EIRE
11
EIRE
10
EIRE
9
EIRE
8
EIRE
7
EIRE
6
EIRE
5
EIRE
4
EIRE
3
EIRE
2
EIRE
1
EIRE
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-6. SIU DMA/Interrupt Request Enable Register (SIU_DIRER)
Table 8-8. SIU_DIRER Field Descriptions
Field Description
EIREn External Interrupt Request Enable n. Enables assertion of the interrupt request from the SIU to the interrupt
controller when an edge triggered event occurs on the IRQn pin.
0 External interrupt request disabled.
1 External interrupt request enabled.
Offset: SI 0x001C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIRS1 DIRS0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-7. DMA/Interrupt Request Select Register (SIU_DIRSR)
Table 8-9. SIU_DIRSR Field Descriptions
Field Description
DIRSn DMA/Interrupt Request Select n. Selects between a DMA or interrupt request when an edge triggered event occurs
on the corresponding IRQn pin.
0 Interrupt request selected.
1 DMA request selected.