NXP Semiconductors PXN2020, Reference Manual, Page: 380 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-16 Freescale Semiconductor
Figure 13-4. Virtual Address and TLB-Entry Compare Process
13.3.1.3 Effective to Real Address Translation
Instruction accesses are generated by sequential instruction fetches or due to a change in program flow
(branches and interrupts). Data accesses are generated by load, store, and cache management instructions.
The instruction fetch, branch, and load/store units generate 32-bit effective addresses. The MMU translates
this effective address to a 32-bit real address which is then used for memory accesses.
Figure 13-5 shows
the effective to real address translation flow.
Figure 13-5. Effective to Real Address Translation Flow
13.3.1.4 Permissions
The application software can restrict access to virtual pages by selectively granting permissions for user
mode read, write, and execute, and supervisor mode read, write, and execute on a per-page basis. For
TLB entry Hit
=0?
private page
shared page
=?
=?
TLB_entry[V]
TLB_entry[TS]
AS (from MSR[IS] or MSR[DS])
Process ID
TLB_entry[TID]
TLB_entry[EPN]
EA page number bits
=?
32-bit effective address
32-bit real address
Virtual Address
PID Effective page address Offset
0 31
TLB
multiple-entry
MSR[IS] for instruction fetch
AS
MSR[DS] for data access
RPN field of matching entry
n–1 n
Real page number Offset
0 31
NOTE: n = 32–log
2
(page size)
n

20
n = 20 for 4 KB page size
n–1 n