NXP Semiconductors PXN2020, Reference Manual, Page: 697 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-83
Figure 26-106. Receive FIFO Structure
26.6.3.4 Message Buffer Configuration and Control Data
This section describes the configuration and control data for each message buffer type.
26.6.3.4.1 Individual Message Buffer Configuration Data
Before an individual message buffer can be used for transmission or reception, it must be configured.
There is a set of common configuration parameters that applies to all individual message buffers and a set
of configuration parameters that applies to each message buffer individually.
Common Configuration Data
The set of common configuration data for individual message buffers is located in the following registers.
• Message Buffer Data Size Register (MBDSR)
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data
field with respect to the message buffer segment.
• Message Buffer Segment Size and Utilization Register (MBSSUTR)
The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual
RFBRIR RFDSR[B] RFSIR[B]
RFARIR RFDSR[A] RFSIR[A]
Frame Header[1] Slot Status[1] Data Field Offset[1]
Receive FIFO Control Register
Message Buffer Header Fields
Message Buffer Data Fields
Frame Header[n] Slot Status[n] Data Field Offset[n]
(min) RFDSR[ENTRY_SIZE] * 2 bytes
R
F
DS
R[
F
IFO
_
D
E
P
TH
]
+
Frame Header[i] Slot Status[i] Data Field Offset[i]
Frame Data[n]
SADR_MBDF[n]
Frame Data[i]
SADR_MBDF[i]
Frame Data[1]
SADR_MBDF[1]
RFDSR
[FIFO_DEPT
H]
SADR_MBHF[n]
SADR_MBHF[i]
SADR_MBHF[1]
Fle
x
Ra
y Memor
y