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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
26-43
26.5.2.33 Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
This register provides configuration, control, and status information related to the generation and access
of the clock sync ID tables and clock sync measurement tables. For a detailed description, see
Section 26.6.12, Sync Frame ID and Sync Frame Deviation Tables.
Table 26-38. SFTOR Field Description
Field
Description
SFTOR
Sync Frame Table Offset — The offset of the Sync Frame Tables in the Flexray Memory. This offset is required
to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.
Base + 0x0044
Write: Normal Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
CYCNUM
ELKS OLKS EVAL OVAL
0
0
SDV
EN
SID
EN
W ELKT OLKT
OPT
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-33. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
Table 26-39. SFTCCSR Field Descriptions
Field
Description
ELKT
Even Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the even cycle tables.
0 No effect.
1 Triggers lock/unlock of the even cycle tables.
OLKT
Odd Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the odd cycle tables.
0 No effect.
1 Triggers lock/unlock of the odd cycle tables.
CYCNUM
Cycle Number — This field provides the number of the cycle in which the currently locked table was
recorded. If none or both tables are locked, this value is related to the even cycle table.
ELKS
Even Cycle Tables Lock Status — This status bit indicates whether the application has locked the even
cycle tables.
0 Application has not locked the even cycle tables.
1 Application has locked the even cycle tables.
OLKS
Odd Cycle Tables Lock Status — This status bit indicates whether the application has locked the odd cycle
tables.
0 Application has not locked the odd cycle tables.
1 Application has locked the odd cycle tables.
EVAL
Even Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the even cycle are valid. The controller clears this status bit when it starts updating the tables, and
sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing).
1 Tables are valid (consistent).
OVAL
Odd Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the odd cycle are valid. The controller clears this status bit when it starts updating the tables, and
sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing).
1 Tables are valid (consistent).
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...