NXP Semiconductors PXN2020, Reference Manual, Page: 1079 / 1376

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 33-11
The PRESC_CONF bits of register CTU_CSR must not be modified while the counters are running. The
counter behavior is not guaranteed if this rule is not respected. Also, it is recommended to program the
CTU_SVR
n registers only when counters are not running.
33.5.4 Trigger Interrupt Request
When a request for trigger output is generated, the flag TRGI in the CTU_CSR register is set. An interrupt
is generated if the TRGIEN bit in the CTU_CSR register is set. If this condition is false, the interrupt
remains pending to be issued as soon as it is enabled. The interrupt status flag can be cleared by writing
‘1’ to the TRGI bit.
33.5.5 Halt Request
Whenever a halt mode entry request is generated (CTU halt bit in the SIU_HLT0 register is set), the
counters are reset. Setting this bit also turns off the clock to the module, shutting it down.
33.5.6 Channel Value
The channel value stored in an event configuration register is demultiplexed to 7 bits and then provided to
the ADC. The mapping of channel number value to the corresponding ADC channel is provided in
Table 33-10 .
So while programming an event configuration register, this mapping has to be taken care of, e.g., if the
channel value of any event configuration register is programmed to 16, it actually corresponds to channel
32 of ADC and conversion occurs for this channel.
Table 33-10. Channel Number Value Mapping
ADC Channel CTU Channel
Channel 0–15 Channel 0–15
Channel 16–31 — not mapped —
Channel 32–47 Channel 16–31
Channel 48–63 — not mapped —
Channel 64–95 Channel 32–64