NXP Semiconductors PXN2020, Reference Manual, Page: 360 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-34 Freescale Semiconductor
The erase operation is resumed by clearing the MCR[ESUS] bit. The flash continues the erase sequence
from one of a set of predefined points. This can extend the time required for the erase operation.
CAUTION
In an erase-suspended program, programming flash locations in blocks
which were being operated on in the erase may corrupt flash core data.
Figure 12-23. Erase Sequence
User mode read state
Write MCR
ERS = 1
Select blocks
Erase interlock write
Step 1
Step 2
Step 3
Write MCR
EHV = 1
High voltage active
Access MCR
DONE
?
Step 4
WRITE
ESUS = 1
Read MCR
DONE = 1
Erase suspend
ERS = 0
User mode read state
PEG = 0
Read MCR
DONE = 1
DONE = 0
Write MCR
ESUS = 0
EHV = 1
Abort
WRITE
EHV = 0
Step 5
Step 6
PEG
?
Success
PEG = 1
Write MCR
Failure
PEG
= 0
Step 7
EHV = 0
Erase
more blocks
Step 8
?
No
Yes
Write MCR
ERS = 0
User mode read state
Step 9
EHV = 0
Write MCR
PGM = 1
Program, Step 2
Go to Step 2
Note: PEG remains valid under this
condition until EHV is set high or
ERS is cleared.
Note: ESUS cannot be cleared while
EHV
= 0. ESUS and EHV cannot
be changed in a single
write operation.
PEG Valid Period