NXP Semiconductors PXN2020, Reference Manual, Page: 408 / 1376

e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
14-10 Freescale Semiconductor
14.3.2.2 Supervisor-Level Registers
The following supervisor-level registers are defined in e200 in addition to the Power Architecture Book E
registers described above:
• Configuration Registers
— Hardware implementation-dependent register 0 (HID0). This register controls various
processor and system functions.
— Hardware implementation-dependent register 1 (HID1). This register controls various
processor and system functions.
• Exception Handling and Control Registers
— Machine Check Syndrome register (MCSR). This register provides a syndrome to differentiate
between the different kinds of conditions which can generate a Machine Check.
— Debug Save/Restore register 0 (DSRR0). When enabled, the DSRR0 register is used to save
the address of the instruction at which execution continues when
se_rfdi
executes at the end of
a debug interrupt handler routine.
— Debug Save/Restore register 1 (DSRR1). When enabled, the DSRR1 register is used to save
machine status on debug interrupts and to restore machine status when
se_rfdi
executes.
• L1 Cache Configuration Register (L1CFG0) is a read-only register that allows software to query
the configuration of the L1 Cache. For the e200z0, this register returns all zeros.
• System version register (SVR). This register is a read-only register that identifies the version
(model) and revision level of the device which includes an e200 Power Architecture processor.
Note that it is not guaranteed that the implementation of e200 core-specific registers is consistent among
Power Architecture processors, although other processors may implement similar or identical registers. All
e200 SPR definitions are compliant with the Freescale EIS specification definitions.