NXP Semiconductors PXN2020, Reference Manual, Page: 895 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-11
29.3.4 Register Descriptions
This section lists the FlexCAN registers in address order and describes the registers and their bit fields.
29.3.4.1 Module Configuration Register (CANx_MCR)
This register defines global system configurations, such as the module operation mode (e.g., low power)
and maximum message buffer configuration. Most of the fields in this register can be accessed at any time,
except the MAXMB field, which should only be changed while the module is in freeze mode.
Table 29-6. ID Table 0–7 Field Descriptions
Name Description
REM Remote Frame. This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID.
0 Remote frames are rejected and data frames can be accepted.
1 Remote frames can be accepted and data frames are rejected.
EXT Extended Frame. Specifies whether extended or standard frames are accepted into the FIFO if they match the
target ID.
0 Extended frames are rejected and standard frames can be accepted.
1 Extended frames can be accepted and standard frames are rejected.
RXIDA Rx Frame Identifier (Format A). Specifies an ID to be used as acceptance criteria for the FIFO. In the standard
frame format, only the 11 most significant bits (3 to 13) are used for frame identification. In the extended frame
format, all bits are used.
RXIDB_0
RXIDB_1 Rx Frame Identifier (Format B). Specifies an ID to be used as acceptance criteria for the FIFO. In the standard
frame format, the 11 most significant bits (a full standard ID) (3 to 13) are used for frame identification. In the
extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received ID.
RXIDC_0
RXIDC_1
RXIDC_2
RXIDC_3 Rx Frame Identifier (Format C). Specifies an ID to be used as acceptance criteria for the FIFO. In both standard
and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received ID.
Offset: Base + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MDIS FRZ FEN HALT
NOT_
RDY
0
SOFT
_RST
FRZ_
ACK
1 0
WRN
_EN
LPM_
ACK
0 0
SRX_
DIS
BCC
W
Reset 1 1 0 1 1 0 0 0 1
1
0 0 1 0
1
0
1
0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
LPRIO
_EN
AEN
0 0
IDAM
0 0
MAXMB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
1
Writes to this bit have no effect, but reads return the written value.
Figure 29-5. Module Configuration Register (CANx_MCR)