NXP Semiconductors PXN2020, Reference Manual, Page: 1048 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-4 Freescale Semiconductor
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• Basic DMA interface
Features currently not supported:
• No support for general call address
• Not compliant to ten-bit addressing
32.1.4 Modes of Operation
There are two operating modes of the I
2
C module: run mode and halt mode. In run mode, I
2
C_ x = 0 in the
SIU_HLT0 register and all functional parts of the I
2
C module are running. In halt mode, I
2
C_ x = 1 in the
SIU_HLT0 register and all clocks to the I
2
C module are disabled.
32.2 External Signal Description
Refer to Chapter 3, Signal Description, for detailed signal descriptions.
32.3 Memory Map and Registers
This section provides a detailed description of all I
2
C registers.
32.3.1 Module Memory Map
Table 32-1 shows the I
2
C memory map. The address of each register is given as an offset to the I
2
C base
address. Registers are listed in address order, identified by complete name and mnemonic.
Table 32-1. I
2
C Memory Map
Offset from
I
2
C_BASE
I
2
C_A = 0xFFF8_8000
I
2
C_B = 0xFFF8_C000
I
2
C_C = 0xC3F8_8000
I
2
C_D = 0xC3F8_C000
Register Access Reset Value Section/Page
0x0000 IBAD—I
2
C bus address register R/W 0x00 32.3.2.1/32-5
0x0001 IBFD—I
2
C bus frequency divider register R/W 0x00 32.3.2.2/32-5
0x0002 IBCR—I
2
C bus control register R/W 0x80 32.3.2.3/32-8
0x0003 IBSR—I
2
C bus status register R/W 0x80 32.3.2.4/32-9
0x0004 IBDR—I
2
C bus data I/O register R/W 0x00 32.3.2.5/32-10
0x0005 IBIC—I
2
C bus interrupt configuration register R/W 0x00 32.3.2.6/32-11
0x0006–0x3FFF Reserved