NXP Semiconductors PXN2020, Reference Manual, Page: 914 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-30 Freescale Semiconductor
executed, the MB remains locked, unless the CPU reads the C/S word of another MB. Only a single MB
is locked at a time. The only mandatory CPU read operation is the one on the control and status word to
assure data coherency (see
Section 29.4.5, Data Coherence ).
The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the
CAN
x _IFLAG registers and not by the code field of that MB. Polling the code field does not work because
after a frame is received and the CPU services the MB (by reading the C/S word followed by unlocking
the MB), the code field does not return to EMPTY. It remains FULL, as explained in
Table 29-4 . If the
CPU tries to work around this behavior by writing to the C/S word to force an EMPTY code after reading
the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly
received frame matching the ID of that MB may be lost. In summary:
never do polling by reading directly
the C/S word of the MBs. Instead, read the CANx_IFLAG registers.
The received ID field is always stored in the matching MB, thus the contents of the ID field in an MB may
change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself
if there exists an Rx matching MB, provided the SRX_DIS bit in the CAN
x _MCR is not asserted. If
SRX_DIS is asserted, FlexCAN does not store frames transmitted by itself in any MB, even if it contains
a matching MB, and no interrupt flag or interrupt signal is generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO during
freeze mode (see
Section 29.4.6, Rx FIFO ). Upon receiving the frames available interrupt from FIFO, the
CPU should service the received frame using the following procedure:
1. Read the control and status word (optional – needed only if a mask was used for IDE and RTR bits).
2. Read the ID field (optional – needed only if a mask was used).
3. Read the data field.
4. Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read the
next FIFO entry).
29.4.4 Matching Process
The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx
MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the
8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the
other MBs are scanned. In the event that the FIFO is full, the matching algorithm always looks for a
matching MB outside the FIFO region.
When the frame is received, it is temporarily stored in a hidden auxiliary MB called serial message buffer
(SMB). The matching process takes place during the CRC field of the received frame. If a matching ID is
found in the FIFO table or in one of the regular MBs, the contents of the SMB are transferred to the FIFO
or to the matched MB during the 6th bit of the end-of-frame field of the CAN protocol. This operation is
called move-in. If any protocol error (CRC, ACK, etc.) is detected, than the move-in operation does not
happen.
For the regular mailbox MBs, an MB is said to be free to receive a new frame if the following conditions
are satisfied:
• The MB is not locked (see Section 29.4.5.3, Message Buffer Lock Mechanism )