NXP Semiconductors PXN2020, Reference Manual, Page: 282 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-14 Freescale Semiconductor
10.3.2.5 INTC Interrupt Acknowledge Register for Processor 1 (Z0)
(INTC_IACKR_PRC1)
10.3.2.6 INTC End-of-Interrupt Register for Processor 0 (Z6) (INTC_EOIR_PRC0)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the
INTC_EOIR_PRC0 is written, the priority last pushed on the LIFO is popped into INTC_CPR_PRC0. An
exception to this behavior is described in
Section 10.1.3.2, Hardware Vector Mode. The values and size of
data written to the INTC_EOIR_PRC0 are ignored. The values and sizes written to this register neither
update the INTC_EOIR_PRC0 contents or affect whether the LIFO pops. For possible future
compatibility, write four bytes of all 0s to the INTC_EOIR_PRC0.
Offset: INTC_BAS 0x0014 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
VTBA_PRC1 (most significant 16 bits)
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA_PRC1
(5 least-significant bits)
INTVEC_PRC1
1
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
When the VTES_PRC1 bit in INTC_MCR is asserted, INTVEC_PRC1 is shifted to the left one bit. Bit 29 is read as
0. VTBA_PRC1 is narrowed to 20 bits wide
Figure 10-13. INTC Interrupt Acknowledge Register for Processor 1 (Z0) (INTC_IACKR_PRC1)
Table 10-7. INTC_IACKR_PRC1 Field Descriptions
Field Description
VTBA_PRC1 Vector Table Base Address for Processor 1 (Z0). VTBA_PRC1 can be the base address of a vector table of
addresses of ISRs for processor 1 (Z0). The VTBA_PRC1 only uses the leftmost 20 bits when the
VTES_PRC1 bit in INTC_MCR is asserted.
INTVEC_PRC1 Interrupt Vector for Processor 1 (Z0). INTVEC_PRC1 is the vector of the peripheral or software settable
interrupt request that caused the interrupt request to the processor. When the interrupt request to the
processor asserts, the INTVEC_PRC1 is updated, whether the INTC is in software or hardware vector mode.
Offset: INTC_BAS 0x0018 Access: User write-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W INTC_EOIR_PRC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W INTC_EOIR_PRC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-14. INTC End-of-Interrupt Register for Processor 0 (Z6) (INTC_EOIR_PRC0)