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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
26-103
Transition Priorities
The application can trigger only one transition at a time. There is no need to specify priorities among them.
As shown in the first part of
, the module transitions have a higher priority than the application
transitions. For all states except the CCMa state, both a lock/unlock transition HL/HD and a module
transition can be executed at the same time. The result state is reached by first applying the application
transition and subsequently the module transition to the intermediately reached state. For example, if the
message buffer is in the HLck state and the application unlocks the message buffer by the HU transition
and the module triggers the slot assigned transition SA, the intermediate state is Idle and the resulting state
is CCSa.
The priorities among the module transitions is given in the second part of
26.6.6.2.4
Transmit Message Setup
To transmit a message over the FlexRay bus, the application writes the message data into the message
buffer data field and sets the commit bit CMT in the
Message Buffer Configuration, Control, Status
. The physical access to the message buffer data field is described in
Section 26.6.3.1, Individual Message Buffers.
MA
slot match and
CycleCounter match
Message Available - Message buffer is assigned to next slot and cycle counter
filter matches.
TX
slot start and
MBCCSRn[CMT] = 1
Transmission Slot Start - Slot Start and commit bit CMT is set.
In case of a dynamic slot, pLatestTx is not exceeded.
SU
status updated
Status Updated - Slot Status field and message buffer status flags updated.
Interrupt flag set.
STS
static slot start
Static Slot Start - Start of static slot.
DSS
dynamic slot start or
symbol window start or
NIT start
Dynamic Slot or Segment Start. - Start of dynamic slot or symbol window or NIT.
SSS
slot start or
symbol window start or
NIT start
Slot or Segment Start - Start of static slot or dynamic slot or symbol window or
NIT.
Table 26-99. Single Transmit Message Buffer Transition Priorities
State
Priorities
Description
module vs. application
Idle, HLck
SA > HD
MA > HD
Slot Assigned > Message Buffer Disable
Message Available > Message Buffer Disable
CCMa
TX > HL
Transmission Start > Message Buffer Lock
module internal
Idle, HLck
MA > SA
Message Available > Slot Assigned
CCMa
TX > STS
TX > DSS
Transmission Slot Start > Static Slot Start
Transmission Slot Start > Dynamic Slot Start
Table 26-98. Single Transmit Message Buffer Module Transitions (continued)
Transition
Condition
Description
Summary of Contents for PXN2020
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