NXP Semiconductors PXN2020, Reference Manual, Page: 592 / 1376

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-26 Freescale Semiconductor
25.3.4.20 FIFO Receive Bound Register (FRBR)
The FRBR is a 32-bit register with one 8-bit field that the user can read to determine the upper address
bound of the FIFO RAM. Drivers can use this value, along with the FRSR register, to appropriately divide
the available FIFO RAM between the transmit and receive data paths.
Offset: FE 0x0144 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X_WMRK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-20. FIFO Transmit FIFO Watermark Register (TFWR)
Table 25-22. TFWR Field Descriptions
Field Descriptions
0–29 Reserved, should be cleared.
X_WMRK Number of bytes written to transmit FIFO before transmission of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
Offset: FE 0x014C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 R_BOUND 0 0
W
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Figure 25-21. FIFO Receive Bound Register (FRBR)