NXP Semiconductors PXN2020, Reference Manual, Page: 1090 / 1376

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-10 Freescale Semiconductor
34.3.2.2 Main Status Register (MSR)
The MSR provides status bits for the ADC.
ACKO Auto clock off enable. If set, this bit enables the Auto clock off feature. See Section 34.4.10, Auto Clock Off
Mode, for more information.
0 Auto clock off is disabled.
1 Auto clock off is enabled.
OFFREFRESH Offset refresh enable. If set, this bit enables the offset refresh feature.
0 No offset refresh.
1 Offset refresh during idle mode when ADC is waiting for a new start of conversion.
OFFCANC Offset Cancellation. This bit is reset to 0 when the offset cancellation ends.
0 No offset cancellation phase.
1 Offset cancellation phase before conversion.
PWDN Power down enable. When this bit is set, the analog module is requested to enter Power Down mode. When
ADC status is PWDN, resetting this bit starts ADC transition to IDLE mode.
0 ADC is in normal mode.
1 ADC has been requested to power down.
Address: AD 0x0004 Access: User read only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0
N
START
J
ABORT
0 0
J
START
0 0 0
CTU
START
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CHADDR 0 0 0 ACKO
OFF
REFR
ESH
OFF
CANC
ADCSTATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 34-3. Main Status Register (MSR)
Table 34-3. MSR Field Descriptions
Field Description
NSTART This status bit indicates that a normal conversion is ongoing.
0 Normal conversion is not occurring now.
1 Normal conversion is occurring.
JABORT This status bit indicates that an injected conversion has been aborted.This bit is reset when a new injected
conversion starts.
0 New injected conversion has been started.
1 Injected conversion has been aborted.
Table 34-2. MCR Field Descriptions (continued)
Field Description