NXP Semiconductors PXN2020, Reference Manual, Page: 301 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-33
NOTE
The peripheral or software settable interrupt request asserts when the PRI n
value in the interrupt priority select register (INTC_PSR n ) is greater than
the PRI n value in interrupt current priority register (INTC_CPR).
If an asserted peripheral or software settable interrupt request negates before
the processor acknowledges its request, the interrupt request can reassert
and remain asserted. If this occurs, the processor uses the INTC_PSR
n value
to locate the IRQ vector, and updates the PRI n value in the INTC_CPR with
the PRI n value in INTC_PSR n .
Clearing the peripheral interrupt request enable bit for the peripheral
initiating the request, or setting the IRQ mask bit has the same consequences
as clearing its flag bit. Setting its enable bit or clearing its mask bit while its
flag bit is asserted has the same effect on the INTC as an interrupt event
setting the flag bit.
10.4.1.1 Peripheral Interrupt Requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
Interrupt requests from devices external to the PXN20 are classified as peripheral interrupt requests in this
reference manual. These type of external peripheral interrupts are handled by the SIU (see
Section 10.4.1,
External Interrupt Request Sources ).
10.4.1.2 Software Settable Interrupt Requests
The software set/clear interrupt registers (INTC_SSCIR x ) support the setting or clearing of
software-settable interrupt requests. These registers contain eight independent sets of bits to set and clear
a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves the
same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just
like a peripheral interrupt request.
An interrupt request is triggered by software by writing a 1 to a SET n bit in
INTC_SSCIR0–INTC_SSCIR7. This write sets a CLR n flag bit that generates an interrupt request. The
interrupt request is cleared by writing a 1 to the CLR n bit. Specific behavior includes the following:
• Writing a 1 to SET n leaves SET n unchanged at 0 but sets the flag bit (CLR n bit).
• Writing a 0 to SET n has no effect.
• Writing a 1 to CLR n clears the flag (CLR n ) bit.
• Writing a 0 to CLR n has no effect.
• If a 1 is written to a pair of SET n and CLR n bits at the same time, the flag (CLR n ) is set, regardless
of whether CLR n was asserted before the write.