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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-138
Freescale Semiconductor
After reading all the data from the locked tables, the application must unlock the table by writing to the
even table lock trigger SFTCCSR.ELKT again. The even table lock status bit SFTCCSR.ELKS is reset
immediately.
If the sync frame table generation is disabled, the table valid bits SFTCCSR[EVAL] and
SFTCCSR[EVAL] are reset when the counter values in the
Sync Frame Counter Register (SFCNTR)
are
updated. This is done because the tables stored in the FlexRay memory are no longer related to the values
in the
Sync Frame Counter Register (SFCNTR)
Figure 26-145. Sync Frame Table Trigger and Generation Timing
26.6.12.5 Sync Frame Table Access
The sync frame tables will be transferred into the FlexRay memory during the table write windows shown
in
. During the table write, the application cannot lock the table that is currently written. If
the application locks the table outside of the table write window, the lock is granted immediately.
26.6.12.5.1
Sync Frame Table Locking and Unlocking
The application locks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT in
the
Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
. If the affected table is not
currently written to the FlexRay memory, the lock is granted immediately, and the lock status bit
ELKS/OLKS is set. If the affected table is currently written to the FlexRay memory, the lock is not granted.
In this case, the application must issue the lock request again until the lock is granted.
The application unlocks the even/odd sync frame table by writing 1 to the lock trigger bit ELKT/OLKT.
The lock status bit ELKS/OLKS is cleared immediately.
26.6.13 MTS Generation
The controller provides a flexible means to request the transmission of the Media Access Test Symbol
MTS in the symbol window on channel A or channel B.
The application can configure the set of communication cycles in which the MTS will be transmitted over
the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the
Configuration Register (MTSACFR)
MTS B Configuration Register (MTSBCFR)
The application enables or disables the generation of the MTS on either channel by setting or clearing the
MTE control bit in the
MTS A Configuration Register (MTSACFR)
. If an MTS is to be transmitted in a certain communication cycle, the application must set
the MTE control bit during the static segment of the preceding communication cycle.
The MTS is transmitted over channel A in the communication cycle with number CYCCNT, if
SFTCCSR.[OPT,SIDEN,SDVEN] write window
even table write
static segment
NIT
static segment
NIT
static segment
NIT
cycle 2n-1
cycle 2n
cycle 2n+1
odd table write
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...