NXP Semiconductors PXN2020, Reference Manual, Page: 280 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-12 Freescale Semiconductor
10.3.2.3 INTC Current Priority Register for Processor 1 (Z0) (INTC_CPR_PRC1)
10.3.2.4 INTC Interrupt Acknowledge Register for Processor 0 (Z6)
(INTC_IACKR_PRC0)
Offset: INTC_BAS 0x000C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
PRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Figure 10-11. INTC Current Priority Register for Processor 1 (Z0) (INTC_CPR_PRC1)
Table 10-5. INTC_CPR_PRC1 Field Descriptions
Field Description
PRI Priority. The function of this register is the same as described for processor 0 (Z6) in Section 10.3.2.2, INTC
Current Priority Register for Processor 0 (Z6) (INTC_CPR_PRC0) .
Offset: INTC_BAS 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
VTBA_PRC0 (most significant 16 bits)
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA_PRC0
(least significant five bits)
INTVEC_PRC0
1
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
When the VTES_PRC0 bit in INTC_MCR is asserted, INTVEC_PRC0 is shifted to the left one bit. Bit 29 is read as
a 0. VTBA_PRC0 is narrowed to 20 bits in width.
Figure 10-12. INTC Interrupt Acknowledge Register for Processor 0 (Z6) (INTC_IACKR_PRC0)