NXP Semiconductors PXN2020, Reference Manual, Page: 696 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-82 Freescale Semiconductor
A receive FIFO consists of a set of physical message buffers in the FlexRay memory and a set of receive
FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 26-106 .
The connection between the receive FIFO control registers and the set of physical message buffers is
established by the
Receive FIFO Start Index Register (RFSIR) , the Receive FIFO Depth and Size Register
(RFDSR) , and the Receive FIFO A Read Index Register (RFARIR) / Receive FIFO B Read Index Register
(RFBRIR) . The system memory base address SMBA is defined by the system memory base address
register selected by the FIFO address mode bit MCR[FAM].
The start byte address SADR_MBHF[1] of the first message buffer header field that belongs to the receive
FIFO in the FlexRay memory is determined according to
Equation 26-5 .
SADR_MBHF[1] = (10 * RFSIR[SIDX]) + SMBA Eqn. 26-5
The start byte address SADR_MBHF[n] of the last message buffer header field that belongs to the receive
FIFO in the FlexRay memory is determined according to
Equation 26-6 .
SADR_MBHF[n] = (10 * (RFSIR[SIDX] + RFDSR[FIFO_DEPTH])) + SMBA Eqn. 26-6
NOTE
All message buffer header fields assigned to a receive FIFO must be a
contiguous region.