NXP Semiconductors PXN2020, Reference Manual, Page: 1374 / 1376

Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
A-116 Freescale Semiconductor
MAS3 MMU Assist Register 3 627
MAS4 MMU Assist Register 4 628
MAS6 MMU Assist Register 6 630
PID0 Process ID Register 48
MMUCSR0 MMU Control and Status Register 0 1012
MMUCFG MMU Configuration Register 1015
TLB0CFG TLB 0 Configuration Register 688
TLB1CFG TLB 1 Configuration Register 689
Cache Registers
L1CFG0 L1 Cache Configuration Register 515
L1CSR0 L1 Cache Control and Status Register 0 1010
L1FINV0 L1 Cache Flush and Invalidate Control Register 0 1016
APU Registers
SPEFSCR SPE APU Status and Control Register 512
Table A-6. e200z6 Core SPR Numbers (User Mode)
Register Description SPR (decimal)
General Registers
CTR Count Register 9
LR Link Register 8
XER Integer Exception Register 1
GPR0–GPR31 General Purpose Registers N/A
Special Purpose Registers
SPRG4 Special Purpose Register 4 260
SPRG5 Special Purpose Register 5 261
SPRG6 Special Purpose Register 6 262
SPRG7 Special Purpose Register 7 263
USPRG0 User Special Purpose Register 256
Timer Registers
TBL Time Base Lower Register 268
TBU Time Base Upper Register 269
Cache Registers
L1CFG0 L1 Cache Configuration Register 515
Table A-5. e200z6 Core SPR Numbers (Supervisor Mode) (continued)
Register Description SPR (decimal)