NXP Semiconductors PXN2020, Reference Manual, Page: 1132 / 1376

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-52 Freescale Semiconductor
Figure 34-51. Request/Acknowledge Timings
34.4.7 Interrupts
The ADC generates the following maskable interrupt signals:
• EOC (End of Conversion) interrupt request
• ECH (End of Chain) interrupt request
• JEOC (End of Injected Conversion) interrupt request
• JECH (End of Injected Chain) interrupt request
• EOFFSET (Error in Offset Cancellation) interrupt request
• OFFCANCOVR (Offset Cancellation Phase Over) interrupt request
• WDG n L and WDG n H (Watchdog Threshold) interrupt requests
Interrupts are generated during the conversion process to signal events such as End of Conversion, etc., as
explained in the register description for ISR. Two registers named ISR (Interrupt Status Register) and IMR
(Interrupt Mask Register) are provided in order to check and enable the interrupt request to the External
Interrupt Control (EIC) module.
The interrupts generated by the analog watchdog are handled by two registers, Watchdog Threshold
Interrupt Status Register (WTISR) and Watchdog Threshold Interrupt Mask Register (WTIMR), in order
to check and enable the interrupt request to EIC module. The watchdog interrupt source sets 2 pending bits
WDG
n H and WDG n L for each of the four channels being monitored in the WTISR register.
In order to reduce the number of interrupt lines, interrupts are combined (ORed) on three lines:
• EOC, ECH, JEOC and JECH on the ADC_EOC line
• EOFFSET and OFFCANCOVR on the ADC_ER line
• WDG0L, WDG0H, WDG1L, WDG1H, WDG2L, WDG2H, WDG3L and WDG3H on the
ADC_WD line
The ISR register contains the interrupt pending request status. In case the user wants to clear a particular
interrupt event status, then writing a ‘1’ to the corresponding status bit clears the pending interrupt flag (at
this write operation all the other bits of the ISR register must be maintained at ‘0’). This is the only write
operation on the ISR and WTISR register. Any other write operation is forbidden, so the registers are
accessible in Read/Clear mode only.
DMA
ADC
ipd_req
ipd_ack