NXP Semiconductors PXN2020, Reference Manual, Page: 1075 / 1376

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 33-7
These registers contain the channel value signifying which channel needs to be ATD converted, the
CLR_FLAG used to clear ocmp flag through software, the counter group that specifies the clock group to
which input channel is associated, the delay selection bits that have to be loaded into the counters and the
mask/enable for the event.
The CLR_FLAG bit has to be used cautiously as setting this bit may result in loss of events.
The event input can be masked by setting trigger mask bit of CTU_EVTCFGR n register to ‘0’.
33.5 Functional Description
The CTU is used to generate a trigger output for the conversion and provide the channel to be converted.
The trigger output is a combination of gated events of different eMIOS/PIT flags with configurable delays.
The trigger output is a single cycle pulse used to trigger an ADC conversion of the channel number
provided by CTU.
Each event has a dedicated configuration register (CTU_EVTCFGR n ). These registers store a channel
number which is used to communicate which channel needs to be converted, the counter group, the start
value selection bits and masking bit for that particular event.
The CTU interfaces between the eMIOS/PIT and the ADC, and convert the events generated by the eMIOS
into ADC conversion requests.
COUNT_
GROUP
Counter Group.
00 Counter 0 is associated with the particular event.
01 Counter 1 is associated with the particular event.
10 Counter 2 is associated with the particular event.
11 Counter 3 is associated with the particular event.
DELAY_
INDEX
Delay Index.
000 No delay is provided.
001 Counter is loaded with value stored in CTU_SVR1.
010 Counter is loaded with value stored in CTU_SVR2
011 Counter is loaded with value stored in CTU_SVR3
100 Counter is loaded with value stored in CTU_SVR4
101 Counter is loaded with value stored in CTU_SVR5
110 Counter is loaded with value stored in CTU_SVR6
111 Counter is loaded with value stored in CTU_SVR7
CLR_FLAG
1
To provide flag_ack through software.
0 Flag_ack is dependent on flag servicing.
1 Flag_ack is forced to ‘1’ for the particular event.
CHANNEL_
VALUE
Channel value to be provided to ADC.
1
This bit implementation is generic based and implemented only for inputs mapped to PIT event flags.
Table 33-8. CTU_EVTCFGRn Register Field Descriptions (continued)
Bit Description