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Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-3
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Initialization (those internal registers not initialized by the user or hardware)
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High level control of the DMA channels (initiating DMA transfers)
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Interpreting buffer descriptors
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Address recognition for receive frames
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Random number generation for transmit collision backoff timer
NOTE
DMA references in this section refer to the FEC’s DMA engine. This DMA
engine is for the transfer of FEC data only, and is not related to the DMA
controller described in
Chapter 24, Enhanced Direct Memory Access
The RAM is the focal point of all data flow in the fast Ethernet controller and is divided into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from
the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the
transmit block and receive data flows from the receive block into the receive FIFO.
The user controls the FEC by writing, through the slave interface module, into control registers located in
each block. The CSR (control and status register) block provides global control (e.g., Ethernet reset and
enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the MDC (management data clock) and MDIO
(management data input/output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data, and
receive descriptor accesses to run independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE
802.3
counters.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...