NXP Semiconductors PXN2020, Reference Manual, Page: 241 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-59
8.3.2.49 Masked Serial GPO Register for DSPI_B Low (SIU_DSPIBL)
The SIU_DSPIBL register allows any combination of bits in the bottom half of the 32-bit serialized data
frame from DSPI_B to be updated with a single 32-bit write operation, while allowing other bits to
maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an
update value contained in a 16-bit output field, and only updating those bits in the output register for which
the corresponding mask bit is set.
Offset: SI 0x0D08 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MASK
31
MASK
30
MASK
29
MASK
28
MASK
27
MASK
26
MASK
25
MASK
24
MASK
23
MASK
22
MASK
21
MASK
20
MASK
19
MASK
18
MASK
17
MASK
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DATA
31
DATA
30
DATA
29
DATA
28
DATA
27
DATA
26
DATA
25
DATA
24
DATA
23
DATA
222
DATA
21
DATA
20
DATA
19
DATA
18
DATA
17
DATA
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-56. Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)
Table 8-35. SIU_DSPIBH Field Descriptions
Field Description
MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_B.
0 The previous value defined by GPO for DSPI_B is maintained.
1 The corresponding GPO for DSPI_B is written with the value defined by the DATAn field.
DATAn Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_B output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_B when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_B when this output is selected in the DSPI
serialization module.
Offset: SI 0x0D0C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MASK
15
MASK
14
MASK
13
MASK
12
MASK
11
MASK
10
MASK
9
MASK
8
MASK
7
MASK
6
MASK
5
MASK
4
MASK
3
MASK
2
MASK
1
MASK
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DATA
15
DATA
14
DATA
13
DATA
12
DATA
11
DATA
10
DATA
9
DATA
8
DATA
7
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-57. Masked Serial GPO Register for DSPI_B Low (SIU_DSPIBL)